P1076 Proposals and Requirements for VHDL-202x

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Language Change Specifications (LCS) for VHDL-202x

After proposals have been reviewed, it's time to write an LCS. This section with collect all produced LCS.

Status Values

  • DRAFT - A LCS is currently written, may change frequently, comments are welcome
  • REVIEW - requesting formal review in working group meeting
  • VOTING - open for voting
  • APPROVED
  • DELAYED
  • REJECTED

LCS Proposal Who Status Description
Deferred from VHDL-2017
LCS-2020-001 Signal map aspect Patrick Lehmann DRAFT Allow a port map and aggregate-like assignment to a <=> connected signal
New LCS
- - Add your LCS here with increasing numbers.

Proposals

Status Values
  • RAW - Initial development, may change frequently, comments are welcome
  • RFC - Draft, needs comments
  • REVIEW - Requesting more formal review in working group meeting
  • STABLE - Done
  • LCS - LCS Editing, Voting, Approval, or Rejection in process
  • Subsumed - subsumed by another proposal/LCS

Rank Item Who Status LCS Description
Deferred from VHDL-2017
- - Deferred Shared Variables Brent Hayhoe RAW - - - - Allow deferred shared variables in packages.
- - Deferred Signals Brent Hayhoe RAW - - - - Allow deferred signals in packages.
- - Allow work in contexts Jim Lewis RAW - - - - Allow work in a context declaration.
- - Multi dimensional slices Patrick Lehmann RAW - - - - Allow slice operations for more then 1 dimension.
- - Operations on integers ?? RAW - - - - Allow boolean and other operations on integers, that have a range as power of two.
- - Hierarchical library names Patrick Lehmann RAW - - - - Allow a hierarchy of libraries in VHDL.
- - Accessing record elements Brent Hayhoe, Patrick Lehmann RAW - - - - Allow handling of records similar to arrays.
- - Subsume IEEE Std. 1076.4 Jim Lewis, Patrick Lehmann RAW - - - - Reactivate IEEE Std. 1076.4 Timing (VITAL) as part of IEEE Std. 1076.
Interface Related Proposals
- - Map functions Jim Lewis RAW - - - - Create a function-like mapping between mode views
- - Signal map aspect Patrick Lehmann RAW - - - - Allow a port map and aggregate-like assignment to a <=> connected signal
Type Related Proposals
- - Derived types Jim Lewis, Patrick Lehmann RAW - - - - Derive integer types (or every scalar type).
- - Derived enumerations Patrick Lehmann RAW - - - - Derive enumeration types.
- - Derived records Patrick Lehmann RAW - - - - Derive record types.
- - Derived protected types Patrick Lehmann RAW - - - - Derive protected types.
- - Records with discriminants Patrick Lehmann RAW - - - - Create typed unions.
- - Protected Type initialization Patrick Lehmann RAW - - - - Add a protected type constructor.
Language Regularizations
- - Optional comma Rob Gaddi RAW - - - - Allow optional commas in lists.
- - Consistent Package API Lars Asplund RAW - - - - Create a consistent API (mainly naming convention).
Testbenches / Continuous Integration
- - Review testbenches Lars Asplund and others RAW - - - - Review existing testbenches.
- - New testbenches Lars Asplund and others RAW - - - - Add more testbenches.
Other Language Enhancements
- - Embedded FSM Language Patrick Lehmann RAW - - - - Add a state machine language.
- - Reflection API - Create values Lieven Lemiengre, Patrick Lehmann RAW - - - - Create and assign values from mirrors at runtime.
- - Range constructor Patrick Lehmann RAW - - - - Allow x downto y to be used to create a range record instance.
LRM Cleanup
- - BNF Clean-up Patrick Lehmann RAW - - - - Clean-up BNF rules.
New Proposals
- - Add your new proposal here
Topic revision: r5 - 2017-04-28 - 13:23:40 - PatrickLehmann
 
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