Multicycle Path

Proposal Information

  • Current Owner: None, ...
  • Contributors: None, ...
  • Date Proposed: 2014-June-22
  • Date Last Updated: 2014-June-22
  • Priority:
  • Complexity:
  • Focus: RTL
  • Related Issues: None
  • Competing Issues: None

Requirement Summary

Speciification of multi-cycle paths in language syntax and works for both simulation and synthesis.

Perhaps capture false paths as well and simulate them

See ISAC IR2003

Related Issues

ClockedShorthand offers several proposed syntax examples to describe multicycle paths.

TimingConstraints proposes the ability to be able to describe timing constraints from within VHDL (including multicycle paths and false paths).

Some initial thoughts that are going no where

For a simulation, a multicycle path with 4 clock delays can be specified with the following, however, this will not help with simulation

process (Clk) 
  if rising_edge(Clk) then 
    AReg <= transport 'X', A after 3 * tperiod_Clk + tpd; 
  end if ; 
end process ; 


TBD What would be better is to use PSL



Topic revision: r4 - 2020-02-17 - 15:34:35 - JimLewis
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