P1076 March 31, 2011 Meeting Minutes

Attendees:

Agenda/Discussion:

Review IEEE patent policy (please read before meeting)

Approve March 17 meeting minutes: Motion: JarekKaczynski 2nd: DavidKoontz

Continue discussion of language change requirements.

Use the Twiki Collected Requirements Page

The twiki page, Requirements List is there for you to edit and add requirements to. Make sure to login to the twiki site first. Basic editing can be done in the Wysiwyg editor and you really don't need to know Twiki to do it. Just edit and save.

The html address of this page is: http://www.eda.org/twiki/bin/view.cgi/P1076/Vhdl2019CollectedRequirements

AI Jim: remind people to post to collected requirements

AI Peter: add stuff on C interface

AI All: Please add things that you have posted to the reflector that you want accumulated and logged for further consideration

Comments on Evan and Jon Bromley comments

Evan and Jon Bromley expressed concern that perhaps 'e' and SystemVerilog are so far ahead that VHDL should not implement verification features.

David Koontz: Updating is technically risky - 2nd

Hans - update or VHDL users will be obliged to switch to other RTL languages eventually.

Jim - Through usage of protected types and package generics, VHDL can already implement data structures, such as scoreboards, FIFOs, memories. I have a first pass at a functional coverage package than can implement much of the capability of SV and e with respect to writing cross coverage and have plans to address issues in future revisions. We can already do procedural randomization, also using packages, and implement many of the language patterns introduced in SV.

One of the concerns expressed by Evan, "Will VHDL200x be used by engineers, or programmers?" I think both and that one of the requirements is that the verification methodology introduced by VHDL be more accessible to hardware engineers.

Other Ideas/Enhancements

David K: Support for unicode - internationalization - character set - how to deal with correctly

Peter - standardize interface between VHDL & Verilog

Peter - Dynamic processes - Application ?? Program sequentially and fork

Jim - Dynamic instantiation with generate?

Library of Components

David Bishop - fairly straight forward

Jim - what enhancements needed to facilitate this? In a previous email I suggested something of the form:

function Mux4 ( Sel : in std_logic_vector(1 downto 0) ; A : in anonymous ; B, C, D : in A'subtype ) return A'subtype ;

David K - anonymous types on ports may require run time checking.

David K - For things like FF, may need internal storage.

Jim - internal storage not available in ordinary subprograms.

Peter - internal storage is provided by protected types

Jim - protected types and hardware design may be challenging to get it implemented.

Decimal Floating Point

David Bishop - 2008 update to FP standard introduced in decimal floating point

VHDL AMS Coordination

David Bishop - matrix packages

AMS - currently doing table driven modeling

AMS - attributes additions

2008 Package Generic Issues

AI: Chuck S and Jerry K to review issues, in particular with packages being created in a general declarative region.

Next Meeting (proposed):

Thursday April 21 at 8 am (3 weeks)

Topic revision: r6 - 2020-02-17 - 15:36:21 - JimLewis
 
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