Sequential Signal Declarations

NOTE 1—It is a consequence of these rules that declarative items appearing within the declarative part of a subprogram body are elaborated each time the corresponding subprogram is called; thus, successive elaborations of a given declarative item appearing in such a place may create items with different characteristics. For example, successive elaborations of the same subtype declaration appearing in a subprogram body may create subtypes with different constraints.

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It doesn't seem possible to dynamically elaborate signals. It would be a terrible simulator complication to be able to add or remove signals and queues from an elaborated design model dynamically.

A process statement (a procedure, not a function which is an expression) communicating to the process through signals requires a process statement that implies hierarchy (a block statement) and promotion of a sequential procedure statement to a concurrent procedure statement.. We already have under utilized block statements. This doesn't appear to be something VHDL needs to support and would require devolving such process statements into block statements and process statements for simulation, essentially expressing that level of hierarchy you're trying to imply but avoid.

-- DavidKoontz - 2014-12-04