IEEE P1076 Working Group

VHDL Analysis and Standardization Group (VASG)


VASG is responsible for maintaining and extending the VHDL standard (IEEE 1076).


VASG is actively working on P1076 2017.

  • Proposal phase
  • Language Change Specifications (LCS) phase
  • Editing phase
    • Edit language changes into the current document
    • Review changes in the document
    • Mandatory Editorial Coordination (MEC)
  • Ballot phases
    • Opened balloting group. Send invitation to register for ballot. (until 15-Apr-2017)
    • Ballot 1
    • Prepare ballot responses
    • Ballot 2
  • Draft phase
    • Final review by IEEE
    • Submit draft to IEEE RevCom (before 16-Oct-2017)

For more information see Working Group Status.


If you are an experienced VHDL user, digital designer, or verification engineer, then this is your working group. Here you can contribute to the future of VHDL.

P1076 is an individual based standard. The only requirement for membership is to show up and participate. Work is done on this TWIKI site, and the email reflector, in our phone meetings. Opportunities to participate are available at many different levels of commitment and your participation will help. Join us.

Meetings & Work Areas



Working Group Administration

Working group officers:


Finding VHDL Standards

VHDL standards are available through IEEE standards association.

  • IEEE 1076: 2008.
    • Older revisions are 2002 (aka: IEC 61691-1-1 Ed.1 (2004-10)), 2000, 1993, 1987
  • IEEE 1076.1
    • 1076.1.1
  • IEEE 1076.2: math_real - subsumed by 1076-2008
  • IEEE 1076.3: numeric_std - subsumed by 1076-2008
  • IEEE 1076.4: VITAL -
  • IEEE 1076.6: VHDL RTL Synthesis 2004, 1999
  • IEEE 1164: std_logic_1164 - subsumed by 1076-2008

Past Projects - VHDL-2008 and Prior

P1076 Web Utilities

The IEEE P1076 Working Group (WG)
Topic revision: r55 - 2017-07-18 - 08:58:38 - JimLewis
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