Active IR List from VHDL-2008

Revised: -- JimLewis - 2014-06-22
Updated links: -- ErnstChristen - 2017-01-05

IRs accepted for consideration in VHDL-201X

These items have been forwarded from ISAC requests to be considered for the next language revision.

IR #	BugZ#	Link to Proposal	Problem to Solve	Description	Notes
2109	-	Enhance	Interface / Com	Semaphore with protected types
2033	-	Enhance		Incremental operator and auto subtype boundary wrap
2108	-	WaitLevel	Testbench Sync	Level sensitive check - A "wait" that checks condition before stopping	Referred to in: Wait with a repeat count
2003	-	MultiCyclePath		Specification of multi-cycle paths to synthesis tool w/o creating registers. Jim Lewis: During meeting how in general specify this and perhaps capture false paths as well and simulate them
2113	-	ReadRom	General	Init ROM / Array data structure with a file - syntax or library (types + std subprogs)
2119	-	DeferredSharedVariables	Interface / Com	Can't declare a protected type and object of that type in a single package
2121	275	Partially Connected Vectors in Port Map	General	Allow for vectors to have assigns and opens in the port map
2125	-	Std_ulogic, Resolved, and '-'	Interface / Com	Resolution of '-' and 'Z' is 'X", ok for RTL, but bad for testbenches?
2007	-	BidirectionalConnections		VHDL needs to be enhanced to allow the modeling of switches. (forward to VHDL-AMS?)
2009	-	ConditionalCompilation		New std package, containing tool and vendor identification information Needs to be considered in conjunction with conditional compilation. May need to be precompiler directives
2011	-	ComponentDerivedFromEntity		Syntax that creates a component declaration from an entity decalaration and puts it into a specified package
2012	-	UniqueCondition		Wants to remove the priority from if-elsif-elsif structures under some conditions. Proposes: "if elsor elsor".
2021	-	DynamicRewiring		Dynamic hardware construct
2025		ConditionalCompilation		"Generate" for sequential code (c.f. ConditionalCompilation)
2106		ConditionalCompilation		Desire preprocessor (macro/ifdef) support in VHDL
2034	-	ClockedShorthand		Introduce history attribute on signals to auto infer registers
2035	-	ClockedShorthand		new function "stages" automates pipelining
2041		Partiallyconnectedvectorsonportmap		Allow composite port subelements to be left open.
2060		Truth Tables		Include truth table for multi-input/multi-output logic.
2072		Operations on Ranges		Allow static operations on "ranges"
2089		Interfaces	Interfaces	Directional records
2100		Operators Overloading for Protected Types		Operator overloading for protected type methods
2076		Record Member Attribute		A member attribute for records.
2065		Relaxed Others Aggregate		OTHERS in aggregates too restrictive
2067		Interfaces		Enhancement: Logical link interface abstraction
2103		DynamicRewiring		Dynamic/run-time creation and destruction of components and connectivity
2130	239	Overload Assignment		Ability to overload the assignment operator := would be useful	Concerns
2132	240	FunctionKnowsVectorSize		Method to allow functions that return arrays to have knowledge of the target attributes
	295	RemoveConfigurationLibraryRequirement		Allow configurations for entities not in the same library
	294	Force and Out Ports		Force of an out port using mode is improperly defined
	293	Alternate Path Name		Issue with path_name and instance_name wrt VHDL-2008 generate labels
	292	ConfigureDirectInstantiation		Configure Architecture of Direct Entity Instantiation
	291	Composites of Protected Types		Allow composites to have elements that are protected types.
	290	Method Parameters that are Access Types		Allow method parameters to be of an access type.
	289	Fix2008ContextClause		Context declaration requirements are not uniform
	288	New Bit Literal Rules		Bit string literals not correctly defined
	287	Process all and global signals		process(all) non-parameter signal read error should be errorenous
	286	Fix2008LRM7321		incremental binding example is illegal
	285	Boolean TEXTIO Write		textio write[line,boolean...] is not backward compatible across language versions
	284	Fixed + Float Pkg updates		Sizing rules for fixed point reciprocal are wrong
	282	Package Name Capitalization		Give IEEE package names consistency capitalization
	281	Fixed + Float Pkg updates		Discrepancies between float_generic_pkg.vhdl and float_generic_pkg-body.vhdl (unresolved_unsigned vs unsigned)
	278 280	Precedence of Unary Logical Operations		Clarify precedence of logic reduction operators
	277	Read of bit_vector vs. std_ulogic_vector		Read of bit_vector and std_ulogic_vector differ slightly.
	276	StopReadOnTrailingUnderscore		'_' at the end of hex and octal reads
	259	User-Defined Attributes May Not Redefine Predefined Attributes		attribute declaration with same designator as a predefined attribute

IRs for 1076.6

IRs Rejected

IR #	BugZ#	Status	Date	Description	Notes
2027	-	Reject	Aug 29, 2013	When loop index is static, drivers are created for each element of array
2131	233	Reject	Email	Vhpi_user.h requires enum types contents update/completion	Information available in parent.
2026	-	Reject	Aug 7, 2014	Upward propagating parameters	VHDL-2008 introduces external names to constants (including generics) that addresses this request. Hence, out generics would be a redundant feature
	283	Reject	May 1, 2014	?/= function in float_generic_pkg can give wrong answer	Resolved as Invalid

IRs Completed in VHDL-2008 by either Accellera VHDL WG or VASG

IR #	BugZ#	Status	Responsible	Description	Notes
2005	-	Done		sla operator behavior does not match typical hardware behavior Base language did not change. Instead it is fixed in packages. It is overloaded in numeric_bit_unsigned for bit vector. For std_logic_vector is not be defined unless numeric_std_unsigned is included.
2117	-	Done		Block comment is not there in vhdl
2118	-	Done, Duplicate		Typo in 9.2 Note 2
2006	-	Done		"else" in "if generate"?
2014	-	Done		Allowance of the keyword "all" in place of a sensitivity list is desirable
2015	-	Done		Generics should be able to incorporate other generics
2016	-	Done, Duplicate		Allowance of the keyword "all" in place of a sensitivity list is desirable
2017	-	Done, Duplicate		Generics should be able to incorporate other generics
2019	-	Done		Reading outputs from within architecture
2022	-	Done		Elements of constant composite to be locally static
2024	-	Done		VHDL needs encryption support
2046		Done		AKA Type Generics: Type independent ports and subprogram parameters
2088		Done		Formatted I/O
2054		Superceded		Individual assoc. rules for array formal are not valid
2063	? 42	Forwarded		Unconstrained array formals should not get subtype from actuals

IRs Completed in VHDL-2008 by ISAC

Original Active IR list dated 18 June 2008