LCS | Proposal | Status | |
---|---|---|---|
LCS-2016-006b | DREAD, DWRITE, Integer D, H, O, B Read and Write | - | 202X |
LCS-2016-006g | Allow access to system environment variables (explorable) | 3 | Need Use Case |
LCS-2016-015b | ReportCallingPath Current File and Line by attributes | 1 | Subsumed by alternative 15a |
LCS-2016-072a | Accessing scalar attributes from within a function: Spinoff from Function Knows Return Vector Size | 12 | Rejected |
LCS-2016-080a | Deferred Shared Variables | 2 | 202X |
LCS-2016-080b | Deferred Shared Variables | 2 | 202X |
LCS-2016-099a | Extension to LCS 099 - intended to make more things locally static | 1 | 202X |
LCS | ISAC ISSUE | Status | |
LCS-2016-I15 | Generate Statement Alternate Path Names - beware of pathname for external names vs RV'path_name | 1 | 202X |
LCS-2016-I15a | Generate Statement Alternate Path Names - Dissenting Opinion | 1 | 202X |
Item | Who | Status | LRM Change Definition | Rank | Description | Final Status | ||
---|---|---|---|---|---|---|---|---|
Interface Related Proposals | ||||||||
Interface and Bundle Enhancements | P1076Group | In Progress | 22 | WG generated interface and bundle enhancements | Alt Done | |||
Partially Connected Vectors on port map | KevinJennings | LCS approved |
1 | Allows a port map vector (array) range slice to be left open. | Done | |||
NewBusModeForBidirectionalPortSignals | BrianDrummond | 40 | Add a "Bus" port mode for bidirectional port signals | Alt Done | ||||
Protected Types with Public Signals | JimLewis | 44 | 202X | |||||
Interface Construct and Port Mode Configurations | BrentHayhoe | LCS in progress | 45 | Alt Done | ||||
Packages as an Interface Construct | JimLewis | 53 | ?? | |||||
Implicit Parameter and Port Connections | JimLewis | - | 54 | Shorthand notation for parameter and port maps | 202X | |||
Bidirectional Connections | KevinCameron | LCS in progress | 70 | Enable modeling of bidirectional components | 202X | |||
Closely related record types | RyanHinton | LCS in progress | 75 | Done | ||||
Converting Things, Generally | ||||||||
Extend IMAGE attribute to arrays and records | Ryan Hinton | LCS in progress | 12 | Extend IMAGE attribute and/or TO_STRING implicit function to composite types: arrays and records. | Done | |||
Record Introspection | ChrisHiggs | LCS in progress | 41 | Convert between a record and a vector | 202X | |||
Record Introspection & Indexing | Brent Hayhoe | LCS in progress | 69 | Proposal to allow indexing and scanning of elements within record structures. MERGED (WAS: Member attribute for records) | 202X | |||
Language Regularization Proposals | ||||||||
Allow access types and protected types on Function Interface | JimLewis | LCS completed |
2 | - | Done | |||
Protected Type Methods with Parameters that are Access Type, Protected Type, or File Type | JimLewis | 4 | Method Parameters with access types | Done | ||||
Sequential Declaration Regions | JimLewis | LCS | 7 | - | Done | |||
Composites of Protected Types | JimLewis | LCS | and | 14 | Arrays and records containing protected types | Done | ||
Protected types and aliases | JimLewis | Subsumed | 17 | Subsumed by LCS-2016-033 | Alt Done | |||
Sizing from initial values | RyanHinton | LCS completed |
19 | Allow signal and variable constraints to be deduced from initial values. This is already allowed for constants, but this proposal extends the capability to variables and signals. | Done | |||
Relax Library Requirement on Configurations | CliffordWalinsky | RFC | 23 | Allow configurations to reside in different libraries from their corresponding entities. | Done | |||
Conditional Expressions and/or Operator | CliffordWalinsky | LCS completed |
36 | Allow the use of conditionals in expressions and initializers. | Done | |||
Syntax regularization - End | JimLewis | LCS complete | 55 | Particularly "End" | Alt Minimal Done | |||
Process-All and Implicit Signals | Brent Hayhoe | RFC | 56 | Allow implicit signals alongside the ALL keyword in sensitivity lists. | 202X | |||
Syntax regularization - Optional Semicolon | BertDeJong | LCS completed |
71 | Extra optional semicolon at end of interface_list | Done | |||
Package Name Case Sensitivity | JimLewis | 79 | 202X | |||||
Syntax regularization - Empty records | RyanHinton | LCS in progress | 82 | Allow record declations to have no members, analogous to a null array | Done | |||
Conditional Return Statement | JimLewis | LCS | 94 | - | Alt Done | |||
Integer Proposals | ||||||||
Integers of arbitrary length | MartinThompson | RFC | KevinJennings: Appended yet another alternate proposal to end of this proposal. Not clear about the current status of any of these integer extending proposals. | 8 | Add integers of arbitrary length | 202X | ||
Long Integers 64 bit type | CliffordWalinsky | LCS completed |
26 | Add a type for 64 bit integers, separate from integer | 202X | |||
Modular Integer Types | MartinThompson | - | KevinJennings: Ditto | 31 | 202X | |||
Additional Operators for Integers - logic | JimLewis | LCS completed |
51 | Add Logic Operators for Integers | 202X | |||
Implicit Conversions for Like Types | JimLewis | 81 | Addresses issues with assigning integer literals to unsigned, signed, real literals to ufixed, sfixed, and float, and vice-versa. Obviously with some constraints. | 202X | ||||
Extended Integers | DanielKho | RAW | KevinJennings: See comments listed for Integers of arbitrary length | Require a minimum of 64 bits for integers. | 202X | |||
Physical Type Range | KevinThibedeau | KevinJennings: Recommend changing this to subsumed based on the much larger integer range defined in LCS-2016-026. | Require that user-defined physical types can cover the same range as time. | 202X | ||||
Enhanced Integers | JonasBaggett | RFC | KevinJennings: See comments listed for Integers of arbitrary length | None | New derived integer types fittable for synthesis. | 202X | ||
Language Enhancement | ||||||||
Date and time system functions | RobGaddi | LCS approved |
11 | Get system date/time and manipulate the results. | Done | |||
Modify Report Statement to return calling path of subprograms | PeterFlake MartinThompson |
15 | 202X | |||||
PATH_NAME and Shared Variables and Subprograms | JimLewis | - | 32 | Done | ||||
Anonymous Types on Interfaces | JimLewis | - | 16 | - | Done | |||
Attributes for Enumerated Types | JimLewis | LCS completed |
18 | - | doen | |||
DPI Proposal | PeterFlake | - | 21 | Direct interface to other languages | 202X | |||
Hierarchical Libraries | ChrisHiggs | - | 25 | library protocol.packet.ethernet | 202X | |||
External names for types | JimLewis | LCS | 28 | See Alternative Proposal. Needed to access the type of a statemachine from tesbench. | 202X | |||
Updates to standard packages - split into LRM and Packages | RyanHinton | RFC | 29 | Additions to LRM, standard, std_logic_1164, numeric_std, math_real, math_complex, and fixed_pkg | 202X | |||
Garbage Collection | CliffordWalinsky | 30 | Garbage collection | Done | ||||
Composition with Protected Types | JimLewis | LCS | 33 | Composition with protected types | Done | |||
Protected Types with Generic Clause | JimLewis | LCS | 34 | - | Done | |||
Configuration Spec for Direct Instances | RyanHinton | RFC | 37 | Add a facility to write a configuration specification to control architecture selection possibly several hierarchy layers deep for a direct instantiation. | 202X | |||
Attributes for PSL | JimLewis | - | 43 | - | 202X | |||
Protected Types with Wait and Private Signals | JimLewis | 46 | 202X | |||||
Protected Type on Entity Interface | JimLewis | 47 | Done | |||||
Map subprogram generics on call | JimLewis | RFC | 49 | - | Done | |||
API for Assert | JimLewis | LCS completed |
50 | - | 202X Extend for Call Path | |||
Slicing Multidimensional Arrays | RyanHinton | 52 | 202X "Streaming Operators"? | |||||
External Non-Shared Variable Name | Brent Hayhoe | RFC | Add the ability to reference local process variables and VHDL93 shared variables via the 'external name' syntax. | 202X | ||||
Array type generics | RyanHinton | LCS in progress | 59 | Indicate that a generic type is an array of another generic type. | Done | |||
New Predefined Attributes: actual, and formal | Brent Hayhoe | LCS completed |
LCS-2016-060 LCS-2016-072a (alternative) |
60 | Allow explicit selection of actual or formal part of an instantiated subprogram's parameter. | 202X | ||
Conditional Compilation | Many | LCS completed |
61 | solve tool-specific language issues | Done | |||
Abstract Packages | JimLewis | - | 62 | - | 202X | |||
Wait with Level Check | JimLewis | 63 | Wait with level sensitive check | 202X | ||||
Unions and/or Variant Records | JimLewis | RAW | 65 | Need unions to describe coverage that can either be a range or a single value | 202X | |||
Expressions in Bit String Literals - Dynamic Sizing | Brent Hayhoe | RFC | Refer to alternative LCS-2016-072a | 66 | Adds the facility to define the bit width of the string literal with an integer expression. | 202X | ||
Required Simulator Resolution | JimLewis | 67 | Need construct or subprogram to specify minimum simulator resolution required by a design unit. It is an error for a simulation to enumerate with larger value. | Withdrawn | ||||
Relaxed OTHERS rules in aggregates | RyanHinton | RFC | 68 | Relax the rules for using OTHERS in array aggregates | 202X | |||
Function Knows Return Vector Size | KevinJennings | LCS completed |
72 | Allows functions to access attributes of the target of the function | Done | |||
Deferred Shared Variables | Brent Hayhoe | LCS completed |
80 | Shared variables & protected types in same package. Clarification of semantics in BNF productions relating to 'subtype indications'. |
202X | |||
Remove Ordering Restrictions on Interface Lists | CliffordWalinsky | LCS completed |
86 | Allow entity and subprogram interface objects to refer to earlier objects of the same interface list. |
Done | |||
Operations on Ranges | Need Owner | LCS in progress |
99 | Support Operations on Ranges | Done | |||
Overload Assignment Operator | OPEN | 102 | Ability to overload the assignment operator := would be useful | 202X | ||||
Extended String Literals | JimLewis, DanielKho | Support C Style String Literals | 202X | |||||
Extended Ranges | PatrickLehmann | RAW | None | Make ranges more powerful. | 202X, Needs new proposal | |||
Extended user-defined attributes | PatrickLehmann | RAW | None | Let users define new attributes, which for example map to functions. | 202X | |||
Unresolved booleans, integers, etc. | DanielKho | Move this to rejected? KevinJennings - 2016-10-31 | Have unresolved versions for boolean, bit, character, and integer | reject | ||||
New proposals | ||||||||
Access to logical representation of VHDL objects | JonasBaggett | RAW | Access to binary representation of VHDL objects via new attributes | 202X, Accepted For Study |
Item | Who | Status | LCS Link | Rank | Description | Final Status |
---|---|---|---|---|---|---|
numeric_std, fixed and float bugs and consistency updates | DavidBishop | 3 | Bug fixes and consistency updates for numeric_std, fixed_generic_pkg.vhd, and float_generic_pkg.vhd |
Ask David | ||
Real Matrix Math Package | DavidBishop | REVIEW | 5, 10, 13 | Matrix Math User's Guide (pdf)![]() Packages (zip) ![]() |
202X | |
Fixed point Algorithmic User's Guide (pdf)![]() |
DavidBishop | REVIEW | Package (zip)![]() |
Open Source Doc | ||
Floating point Algorithmic User's Guide (pdf)![]() |
DavidBishop | REVIEW | Package (zip)![]() |
Open Source Doc | ||
File IO / TextIO updates | JimLewis | LCS in complete |
6 | - | Done | |
Flag metavalues detected by ?? | JimLewis | 9 | 202X | |||
Read differences of bit_vector and std_logic_vector | JimLewis | 27 | 202X Review | |||
Updates to standard packages - split into LRM and Packages | RyanHinton | RFC | 29 | Note this is listed here and in enhancements. Additions to LRM, standard, std_logic_1164, numeric_std, |
202X Review |
Item | Who | Status | LRM Change Definition | Rank | Description | Final Status | |
---|---|---|---|---|---|---|---|
P1735 Encryption Updates | JarekKaczynski JohnShields |
STABLE | I1 | Adopt Recommendation from P1735 | Done | ||
P1735 Visibility Updates | StevenDovich | I2 | Alignment with P1735 visibility model | Done | |||
Signatures for Association List Aspects | CliffordWalinsky | RFC | I3 | Describes how to resolve ambiguous mappings of subprograms to overloaded interface subprograms in generic map aspects. |
-- | ||
Assigning 2008 Entities to Attribute Classes | CliffordWalinsky | RFC | LCS-2016-I04 | I4 | Describes how subprogram instances, interface subprograms, package instances and interface packages match entity classes in attribute specifications. |
-- | |
Repair LRM Example 14.2 | CliffordWalinsky | LCS completed |
I5 | Fix for one of the examples in LRM Section 14.2. | -- | ||
Repair LRM Example 7.3.2.1 | DanielKho | LCS completed |
I6 | Fix the example in 7.3.2.1. | -- | ||
Repair Text on Context Clauses | DanielKho | RFC | LCS-2016-I07 | I7 | Fix the LRM's text for context clauses. | -- | |
Repair LRM Section 16.8.2.4.3 Missing Paragraph Text | BrentHahoe | LCS completed |
I8 | Correct section header numbering in VHDL 2008 LRM. | -- | ||
Repair example in LRM section 5.6.3 | TristanGingold | LCS completed |
I9 | Fix example in 5.6.3 | -- | ||
Bit String Literals Corner Cases\ | TristanGingold | LCS completed |
I10 | Fix minor issues in 15.8 | -- | ||
Repair Generate Statements | TristanGingold | LCS-2016-I11 | I11 | Fix wording and feature | -- | ||
Force an Out Port | Many | LCS-2016-I12 | I12 | -- | |||
Precedence of Unary Logical Operators | JimLewis | I13 | Why is this a 'Must Do' item? The proposal is proposing that operator precedence should be 'different' than listed in the standard. Precedence in the LRM doesn't appear to be 'wrong', just not what the author of the proposal would want. -- KevinJennings - 2016-12-01 |
Done | |||
String representation for extended identifiers | PeterFlake | LCS completed |
I14 | -- | |||
Alternate Label in Path Name bug 293 | PeterFlake | LCS completed |
I15 | -- | |||
Repair Example in Section 23.21 Proposal | RadoslawNawrot | LCS completed |
I16 | Fix for LRM VHPI example | -- | ||
Typographical Issues in IEEE Std 1076-2008 | Many | I17 | A collection of typographical issues in the LRM that don't have a separate page | -- | |||
Process-All Should Not Be Sensitive to Signals in Packages | RobGaddi | LCS completed |
I18 | Ranking: 87 - Designs are in error if they have a process(all) block that calls a package's subprogram that references a signal. Since this error is costly to accurately verify, remove this requirement. |
-- | ||
PSL Harmonization | AjeethaKumari | Done | |||||
Item | Who | Status | Last Modified | Description | Status |
---|---|---|---|---|---|
Table Driven Modeling | Joachim Haase et.al. | Forwarded to Open Source Group |
5/24/2012 | The package supports the description of functional dependencies y = f(x1, x2, ..., xn) based on a number of (n+1)-tupels (y, x1, x2, ..., xn). Emphasis is on floating point functions, and various interpolation schemes are supported. More details, and a reference implementation can be found in a protected area of the P1076.1 web. | 202X |
Vector/matrix package | David Bishop, Zhichao Deng | Forwarded to Open Source Group |
It's the same package listed in the next table | 202X |
Item | Who | Status | Last Modified | Description | Supporters Priority |
---|---|---|---|---|---|
FSM Safe Design | Brent Hayhoe | RFC | Proposal to allow safe state identification for synthesis in FSM designs. | ||
Synthesis Attributes | Attributes for RAM, ROM, ... Define these in 1076? | ||||
Assertions as Directives | main.JimLewis | Support ZeroOneHot, ... | |||
SupportReal | |||||
Synthesizable 'event | |||||
Item | Who | Status | Last Modified | Description | Supporters Priority | |
---|---|---|---|---|---|---|
File IO for RTL ROM | JimLewis | Forwarded to Open Source Group |
Ranking: 24 - File IO for RTL ROM | |||
Functional Coverage | JimLewis | Forwarded to Open Source Group |
Implemented by open source group OSVVM![]() |
|||
Random Stimulus | JimLewis | Forwarded to Open Source Group |
Implemented by open source group OSVVM![]() |
|||
Semaphores | ||||||
Extended Hardware Functions - RTL Macros | Forwarded to Open Source Group |
RTL Macros. Meeting: Dec 15, 2011 and Mar 31, 2011 | ||||
Associative Arrays | Forwarded to Open Source Group |
See TBV Propoal 2 | ||||
Queues / FIFO | Forwarded to Open Source Group |
See TBV Proposal 4 | ||||
Sync and Handshaking | Forwarded to Open Source Group |
See TBV Proposal 7 | ||||
Memory / Sparse array | Forwarded to Open Source Group |
See TBV Proposal 12 | ||||
Loading and Dumping Memories | Forwarded to Open Source Group |
See TBV Proposal 18 | ||||
Lists | Forwarded to Open Source Group |
See TBV Proposal 19 | ||||
Create open source boost/C++ like libraries | Meeting: Dec 15, 2011 | |||||
to_integer and to_integer_vector | JimLewis | - | - | |||
Graphics Library | DanielKho | Forwarded to Open Source Group |
Implement a graphics library for VHDL. | |||
Regular Expressions | DanielKho | Forwarded to Open Source Group |
Implement VHDL regular expressions. | |||
Item | Who | Status | Rank | Description | Status | |
---|---|---|---|---|---|---|
VHPI Impact | VHDL-2008 & VHDL-2019 impact to VHPI | Low Priority | ||||
VHPI for PSL | PSL impact to VHPI | Low | ||||
define parameters for env.stop | OPEN | Define standard parameters for env.stop | 202X | |||
Standard Instances of Float | OPEN | Define standard instances of float_generic_pkg and fixed_generic_pkg | Low | |||
Vector literal introspection | JimLewis | RFC | 35 | Distinguish between std_logic_vector and integer_vector literals | Low | |
Object Orientation | 39 | Links to different proposals | Low | |||
Wait with a repeat count | JimLewis | - | 48 | - | 202X | |
CrossLanguageInstances | 73 | Related to DPI | 202X | |||
Std_ulogic, Resolved, and '-' | JimLewis | 74 | Resolution of '-' and 'Z' is 'X", ok for RTL, but bad for testbenches? | Reject | ||
Create natural_vector | JimLewis | 78 | Create natural_vector as a subtype of integer_vector | 202X | ||
Architecture Generic | LarsJensen | RFC | 83 | Implements architecture instantiation through generics | Low | |
Multiple Top-Level Designs | CliffordWalinsky | Needs Work & Advocate |
88 | Allow designs to have multiple top-level roots. To be a common enhancement, it needs someone with a use case to work on it. Only concerns are about paths in both external names and attributes: 'INSTANCE_NAME 'PATH_NAME |
202X | |
Preponed Processes (clocks) | JimLewis | - | 89 | Desc | 202X | |
Update std_logic_arith | JimLewis | 90 | Update std_logic_arith to simplify interoperability with numeric_std
|
202X Low |
||
Dynamic Process, Instances, Fork Join | 91 | Low | ||||
Shorthand Subprogram Declarations | JimLewis | - | 92 | - | Low | |
Sequential Signal Declarations | JimLewis | - | 93 | - | 202X | |
Truth Tables | Need Owner | 98 | Truth table for multi-input/multi-output | Low | ||
Asynchronous Channels | KevinCameron | 100 | Asynchronous channels (aka pipes) | Low | ||
Clocked Shorthand | DanielKho | RFC | 103 | Shorthand to infer flip-flops and pipelining Z <= A when rising_edge(Clk) ; process(A, Clk) begin if rising_edge(Clk) then Z <= A ; end if ; end process ; Z <= A when Sel = '1' else B ; |
Open Source Group? | |
Dynamic Rewiring | KevinCameron | 105 | Allow runtime re-elaboration and re-wiring | |||
Composing Paths to External Names | JimLewis | 202X | ||||
Attribute Shorthand | DanielKho | RAW | Shorthand to create attributes. | |||
Support Synthesis of Reals | DanielKho | RAW | Simplify synthesis of floating-point operations, by using real to encapsulate synthesizable fixed- or floating-point types. | Synthesis | ||
Item | Who | Status | Rank | Description | StatusPriority | |
---|---|---|---|---|---|---|
2008 Boolean Write | JimLewis | Rejected | Case sensitivity and now what? | Rejected | ||
Predefined Attributes Can't Be Redefined | CliffordWalinsky | RFC | 42 | Prohibit predefined attributes from being redefined. | Reject | |
Named Package Bodies | JimLewis | - | 64 | - | 202X | |
Unique Condition - OrIf | PeterFlake | 76 | 202X | |||
Synthesizable Reports and Assertions | DanielKho | RFC | 77 | Allow assertions to count in synthesis Emulator behavior Reporting to the synthesis log? Check generic values are appropriate? Compile time assertions? |
Synthesis | |
Simulation Controls | 84 | Some is probably done | Reject | |||
Additional Rules for Bit String Literals | DanielKho | RFC | 85 | Specify additional rules for string literals. | Reject | |
Recommend Error Messages | ChrisHiggs | - | 95 | Standard format for error messages | Reject | |
Mixed Signal Support | KevinCameron | 96 | Support multiple types driving/receiving on a wire | 1076.1 Reject | ||
Multicycle Path Specification | 97 | Speciification of multi-cycle paths in language syntax | Synthesis | |||
AtomicComposites | Needs Owner | 101 | Reject | |||
Operators Overloading for Protected Types | Need Owner | 104 | Can already do this with 2019 since impure functions allow PT as an operand. Although this is a different implentation of the requirement. | Done | ||
2 and 4 State values | Needs Owner | 108 | Derived / constrained type that automatically and can be controlled during simulation elaboration. | 202X | ||
Specifying Timing Constraints | DanielKho | RAW | Allows RTL designers to specify timing constraints directly from HDL. | Synthesis | ||
Synthesizable 'event Attribute | DanielKho | RAW | Synthesize 'event for DDR FFs. | Synthesis | ||
Object Inspection | JingPang | RAW | Method to do introspection on names, find different objects and find all instance labels whose component is xyz. | see VHPI | ||
Use of Unicode | MartinThompson | Reject | Add unicode for strings, files, identifiers, comments | 202X - Issue, UFT8 - How do we size strings - one character may require multiple multiple UTF8 characters. Current scope prevents multibyte issues. See python 3 when switched to unicode. | ||
Scope of Keywords | JimLewis | Reject | Give names same scope as keywords | Reject | ||
Component Declaration derived from Entity Declaration | JimLewis | Reject | Not necessary if we can configure a direct entity instantiation. | Reject | ||
Move definition of TEXT, INPUT, OUTPUT | Reject | Could have a context declaration that does: Context IO is use std.textio.text ; use std.textio.OUTPUT; use std.textio.INPUT; end context; |
202X | |||
Stop Binary/Octal/Hex Read At Trailing Underscore | CliffordWalinsky | RFC | 38 | Test results from GitLab![]() |
202X Review implementation and LRM text. | |
Rejected Items from ISAC List | ||||||
Fix generic map rules | TristanGingold | Rejected | I19 | generic-mapped packages are used by package instances | Reject | |
Item | Who | Status | Description | Supporters Priority | ||
---|---|---|---|---|---|---|
Record Indexing | Brent Hayhoe | Subsumed | See:- Record Introspection & Indexing | |||
Signal Pools | KevinCameron | Ranking: 106 - Alternative to wire-like communication for RF | ||||
User Defined IO Rules | KevinCameron | Ranking: 107 - Move rules about in/out/inout to types | ||||
Withdrawn: Functions Know Output Subtypes | OPEN | RFC | Allows function to access subtype properties of the target. | |||
Redundant: Syntax regularazation Entity Component | OPEN | Syntax regularazation between entity and component | ||||
Protected Type Updates | JimLewis | - | Numerous |
List | Description | Notes |
---|---|---|
ISAC Active IR List | ||
Old Meeting Action Item List | Current Action Items now tracked in meeting minutes | |
Bugzilla List![]() |
||
IEEE VHDL 2008 Subgroup Lists (TBV, FT, DTA, ) | ||
Accellera VHDL 2008 Remaining Items List | ||
Raw Requirements in Text of Original Page |
I | Attachment | Action | Size | Date | Who | Comment |
---|---|---|---|---|---|---|
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Accellera_RequirementsStatus_19May2006.xls | manage | 131.0 K | 2011-09-08 - 15:09 | JimLewis | Accellera Requirements List from VHDL-2008 |
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Corrections_to_the_Encryption_Flow_description_in_IEEE_Std_1076.pdf | manage | 204.8 K | 2012-03-15 - 15:10 | JarekKaczynski | Based on the works of P1735 group |
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Proposal.txt | manage | 2.8 K | 2013-08-28 - 17:27 | DavidBishop | Instructions to fix bugs in "fixed_generic_pkg-body.vhdl", "float_generic_pkg-body.vhdl" and the fixed point documentaiton |
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TbIntegerRange.vhd | manage | 2.0 K | 2016-12-23 - 18:54 | JimLewis | IntegerRanges and expressions - where do the bounds apply |
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ft10A_nnary.pdf | manage | 108.2 K | 2016-12-22 - 16:05 | JimLewis | |
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ft10_assignment_ternary.pdf | manage | 183.0 K | 2016-12-22 - 16:05 | JimLewis | VHDL-2008 proposal for conditional expressions using when |
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vhdl_requirements_priority.xlsx | manage | 16.1 K | 2014-11-13 - 21:17 | JimLewis | VHDL Requirements Prioritization Sheet |