Welcome to the VerilogAMS Work Group

The Verilog-AMS Technical Subcommittee has been created under the auspices of Accellera with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language. This activity has resulted in the Accellera approval of the Verilog-AMS LRM, version 2.3.1, in June 2009. This version supersedes the OVI Verilog-A LRM (from June 1996) and previous versions of the Verilog-AMS LRM. read more.....

Working Group Information

This TWiki site is used as a repository for various documents and examples.

Administration details, confernence call information, and email distribution lists can be found on the main page at: http://www.accellera.org/apps/org/workgroup/v-ams/

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