Subsume IEEE Std. 1076.4 - Timing
Proposal Details
| Authors | Jim Lewis, Patrick Lehmann |
|---|---|
| Date Proposed | 2017-04-28 |
| Last Updated | 2017-04-28 |
| Focus | simulation |
| Dependencies | |
| LCS | TBD |
Summary
IEEE Std. 1076.4-2000 - Timing is currently withdrawn, but heavily used by the community. It should be reactivated.Current Situation
IEEE Std. 1076.4-2000 - Timing (aka. VITAL) is currently withdrawn (see standards status page
.
IEEE Std. 1076 should subsume the standards text and include the VITAL packages.
Requirement
Extend the PAR for VHDL-2020 to allow subsuming 1076.4.Use Cases
- Post synthesis, post place&route simulation libraries offered by FPGA synthesis tools.
- External RAM models offered by Free Model Foundry (FMF)
Implementation details
Integrate Standards text from 1076.4 as new section(s)
Include VITAL Packages
Fix VITAL Packages
The VITAL packages contain invalid VHDL-2008/2017 code: impure functions called by pure functions.Arguments FOR
Arguments AGAINST
General Comments
Supporters
- Jim Lewis
- Patrick Lehmann
- Add your signature here to indicate your support for the proposal
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Topic revision: r1 - 2017-04-28 - 13:22:53 - PatrickLehmann
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