Record Types with Discriminates

Proposal Details

Authors Patrick Lehmann
Date Proposed 2017-04-03
Last Updated 2017-04-03
Focus simulation and synthesis
Dependencies Mode views with discriminates
LCS TBD

Summary

Discriminates are generics for records. In a basic version the allow to constrain a record types. This feature is not very interesting, because VHDL supports unconstrained record types, which can be constrained at any place. Moreover, a subtype can be declared to create a constrained subtype of a unconstrained record type.

A more advanced version of discriminates allows to selectively declare record elements based on a generic value. This would enable VHDL to use statically types unions.

We need the ability to size unconstrained port objects in a parameterized way that does not create a new type - like a generic would.

Alternatively, with generics on a Record which is on an interface, generics create a new type. Does the interface allow an uninstantiated Generic RecordType on the interface which connects to a instantiated type of the actual. -- Same question for Protected Types.

Current Situation

Describe the current situation in this section.

Requirement

Features:
  • Allow types and any discrete value as a generic parameter

Use Cases

Instead of creating multiple wrappers per off- or on-chip bus connection, a discriminate record (union) could be used to implement multiple bus interfaces per IP core (entity).

Examples:

  • Gigabit Ethernet PHY interface: GMII, RGMII, SGMII
  • On-Chip RAM could provide these bus interfaces: native, AMBA4 AXI Lite, WishBone, PLB, Avalon
  • FIFOs could provide these bus interfaces: native, AMBA4 AXI Stream, Xilinx LocalLink, WishBone, PoC.Stream

Gigabit Ethernet Example

-- 3 different physical interface from FPGA to a 1GbE PHY chip
type BusInterfaceKind is (RGMII, GMII, SGMII);

-- Ada style
type NET_PCB_IF (kind : BusInterfaceKind) is record
  case kind is
    when RGMII =>
      TX_Data  : std_logic_vector(4 downto 0);
      RX_Data  : std_logic_vector(4 downto 0);
    when GMII =>
      TX_Data  : std_logic_vector(7 downto 0);
      TX_Valid : std_logic;
      TX_Error : std_logic;
      RX_Data  : std_logic_vector(7 downto 0);
      RX_Valid : std_logic;
      RX_Error : std_logic;
    when SGMII =>
      TX_P     : std_logic;
      TX_N     : std_logic;
      RX_P     : std_logic;
      RX_N     : std_logic;
  end case;
  MDIO_Clock : std_logic;
  MDIO_Data  : std_logic;
end record;

entity Ethernet is
  generic (
    PHY_BUS_KIND : BusInterfaceKind
  );
  port (
    Clock  : std_logic;
	
    PHY_IF : NET_PCB_IF
  )

Implementation details

  1. Allow a generic clause in a record declaration
  2. Allow a special if and case statement in a record declaration
    • declare record members based on the active if or case branches.

Code Examples

Styles off how to define the discriminate

Ada style

type NET_PCB_IF (kind : BusInterfaceKind) is record
  case kind is
    when CHOICE_1 =>
      element_1 : type1;
    when CHOICE_2 =>
      element_2 : type2;
  end case;
end record;

VHDL style 1

type NET_PCB_IF is record
  generic (
    kind : BusInterfaceKind
  );

  case kind is
    when CHOICE_1 =>
      element_1 : type1;
    when CHOICE_2 =>
      element_2 : type2;
  end case;
end record;

VHDL style 2

type NET_PCB_IF is record (kind : BusInterfaceKind) of
  case kind is
    when CHOICE_1 =>
      element_1 : type1;
    when CHOICE_2 =>
      element_2 : type2;
  end case;
end record;

Arguments FOR

  • Ada has it
  • Creating one wrapper per bus interface creates a lot of entities and deep nesting in the design hierarchy. Unions decrease that problem.
  • Works well with mode views if the get discriminates too.

Arguments AGAINST

General Comments

Supporters

  • Patrick Lehmann
  • Add your signature here to indicate your support for the proposal

Topic revision: r2 - 2020-07-05 - 20:24:24 - JimLewis
 
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