Proposal Details

• Who Updates: Jing Pang
• Date Proposed: 2015-7-15
• Date Last Updated: 2015-7-15
• Priority:
• Complexity:
• Focus:

Current Situation

WG meeting 2016-0907: reject - need more relevant examples

Requirement

Use a method "instanceof" combined with attribute, pointer and level of hierichy

features for object instrospection.

Implementation details

Syntax:

1). (intanceof(entity_name)'class_name->object_name, level_number)

This returns '1' to represent the intropection success.

This returns '0' to represent the intropection failure.

2). (intanceof(entity_name)'class_name->all, level_number)

This displays all names

Allowed class_name:

port, architecture, signal, process, process_label,

instance_label, function, procedure

Level_number: 0 indicate current top hierarchical level;

1 indicate 1 level lower than the top hierarchical level;

2 indicate 2 levels lower than the top hiearchical level;

etc.

Code Examples

Half Adder:     

library ieee;
use      ieee.std_logic_1164.all;

entity ha is 
    port( a, b:  in std_logic;  
             cout, s: out std_logic);
end ha;

architecture dataflow of ha is
begin
          s      <=  a   xor  b;
          cout <=  a  and  b;
end dataflow;


Full Adder:
library ieee;
use      ieee.std_logic_1164.all;

entity fa is 
    port( a, b, cin:  in std_logic;  
             cout, s: out std_logic);
end fa;

architecture fa_beh of fa is
signal  sm, p, q:     std_logic;

component ha 
    port( a, b:      in   std_logic;  
             cout, s: out std_logic);
end component;

begin
         u1:   ha  port map(a=>a,   b=>b,    cout=> p, s=> sm );
         u2:   ha  port map(a=>sm, b=>cin, cout=> q, s=> s );
         cout <= p or q;

end   fa_beh;

Testbench for Full Adder Design:

library ieee;
use      ieee.std_logic_1164.all;

entity test_fa is    
end test_fa;

architecture beh of test_fa is

component fa  
    port( a, b, cin:   in    std_logic;  
             cout, s:    out  std_logic );
end component;

signal  a, b, cin, cout, s:     std_logic;

begin
        uut:   fa  port map( a => a,  b=> b, cin=> cin, cout => cout, s=>s);
 
        process
        begin
             a  <= '0';    b<='0';   cin <= '0';
             wait for 10 ns;
        a  <= '0';    b<='0';   cin <= '1';
             wait for 10 ns;
        a  <= '0';    b<='1';   cin <= '0';
             wait for 10 ns;
            
            -- Pseudocodes are shown below
            --$display( intanceof(entity_name)'class_name->object_name, level_number ) 
            --$display( intanceof(entity_name)'class_name->all,        level_number )        
            -- Pseudocode 
              $display(intanceof(fa)'port->a, 1);                --  This resturns '1' to indicate a is a port for full adder
              $display(instanceof(test_fa)'instance_label->uut, 0);  --  This resturns '1' to indicate uut is an instance label
              $display(instanceof(fa)'port->all, 1);           --  This returns all port names of  a, b, cin, cout, s.
             
 
             wait;
        end process;

end beh; 

Use Cases

Testbench Simulation, Design Verification, etc.

Arguments FOR

Arguments AGAINST

General Comments

Supporters

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