VHDLProposals < P1076

P1076 Web>VHDLProposals (2021-05-16, UnaiCorral) (raw view)EditAttach
---+!! P1076 Proposals and Requirements for VHDL-202x

%RED% *This page contains the backlog from 1076-2019.* %ENDCOLOR%

*%RED%Do NOT create new items/entries in these tables. %ENDCOLOR%*

<strong>%RED%All new proposals/requests are tracked through issues in GitLab repository [[https://gitlab.com/IEEE-P1076/VHDL-Issues][IEEE-P1076/VHDL-Issues]].%ENDCOLOR%<br /></strong>
---++!! Sections:

%TOC%

---
---++ Active Proposals for VHDL-202x

If not clear, edit the table in RAW mode.  

| *Status Values* ||
| *-DRAFT | Proposal/LCS Underdevelopment. Comments Welcome |
| *-REVIEW | Proposal/LCS call for comments |
| *-VOTE | Proposal/LCS open for voting |
| *-APPROVED | Proposal/LCS Approved. If Proposal, it's waiting for LCS |
| *-REJECTED | Proposal/LCS Rejected |
---+++ Interfaces
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/100][#100]] | [[SignalMapAspect][Signal map aspect aka: SpaceShip]] . [[BidirectionalConnections][Bidirectional Connections]] | Failed | [[Main.PatrickLehmann][Patrick Lehmann]] | Associate signals together using =&lt;=&gt;= | Failed: [[LCS2016_070][LCS-2016-070]] . [[TopLCS2016_070a][LCS-2016-070a]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/154][#154]] | [[MapFunctions][Map functions]] | RAW | [[Main.JimLewis][Jim Lewis]] | Create a function-like mapping between mode views | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/155][#155]] | null mode for composite interface element actual /formal isolation | Status | Who | Description | [[TopLCS2016_045b][LCS-2016-045b]] |
---+++ General Language
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/10][#10]] | [[DpiProposal][DPI Proposal]] | Status | Main.PeterFlake  | Direct interface to other languages | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/103][#103]] | [[AbstractPackages][Abstract Packages]] | Status | Main.JimLewis  | Description | TBD |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/104][#104]] | [[ConfigureDirectInstantiation][Configuration of Direct Instances]] | Status | Main.RyanHinton | Add a facility to write a configuration specification to control architecture selection possibly several hierarchy layers deep for a direct instantiation.  | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/105][#105]] | 'access attribute to PT  | Status  | Who  | Description  | [[TopLCS2016_014b][LCS-2016-014b]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/106][#106]] | [[WaitLevel][Wait Level - Syntax Solution]]  | Updated for 202X | Who | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/107][#107]] | [[ExpressionsAndSignalParameters][Signal Expressions in Signal Parameter Map]]  | Status | Who | Description | [[TopLCS2016_063][LCS-2016-063]]  |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/108][#108]] | [[SliceMultidimensionArrays][Slicing Multidimensional Arrays]] | Status | Main.RyanHinton | Allow slice operations for more then 1 dimension. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/109][#109]] | [[HierarchicalNamespaces][Hierarchical Libraries]] | Status | Main.PatrickLehmann | [[TopLCS2016_025][LCS-2016-025]] Allow a hierarchy of libraries in VHDL: protocol.packet.ethernet | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/110][#110]] | [[ImplicitConnections][Implicit Parameter and Port Connections]] | Status | Main.JimLewis  | Shorthand notation for parameter and port maps | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/111][#111]] | [[IsPortConnected][Add a method to determine if an output port is connected]] | Status | DaveG - StackOverflow | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/112][#112]] | AssertApiExtension | Status | Who | Extend Assert API to activate Call Path | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/113][#113]] | [[ExpressionsInBitStringLiterals][Expressions in Bit String Literals - Dynamic Sizing]] | Status | [[Main.BrentHahoe][Brent Hayhoe]] | Adds the facility to define the bit width of the string literal with an integer expression. | See alternative [[TopLCS2016_072a][LCS-2016-072a]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/114][#114]] | [[SequentialSignal][Sequential Signal Declarations]] | Status | Main.JimLewis  | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/115][#115]] | [[ComposingExteranlPathName][Composing Paths to External Names]] | Status | Main.JimLewis  | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/116][#116]] | [[CrossLanguageInstances]] | Status | Who | Related to DPI  | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/117][#117]] | [[MultipleDesignHierarchies][Multiple Top-Level Designs]] | Status | Main.CliffordWalinsky | <p>Does this require a change? Does the LRM allow this now?</p> <p>Only concerns are about paths in both external names and attributes: 'INSTANCE_NAME 'PATH_NAME</p> | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/102][#102]] | Sequential declarations in "if", "case", or "loop" | Status | Who | Description | failed: [[LCS2016_007a][LCS-2016-007a]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/118][#118]] | Allow work in context clause  | Status | Who | Potentially conflicts with [[TopLCS2016_I07][LCS-2016-I07]] | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/119][#119]] | [[Fix2008ContextClause][Fix 2008 Context Clause]]  | Status | Who | Potentially conflicts with allow work in context clause | [[TopLCS2016_I07][LCS-2016-I07]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/120][#120]] | [[AliasDesignUnit][Aliases to Design Units - ie renaming packages]] | Status | Main.PatrickLehmann | Direct interface to other languages | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/121][#121]] | [[PreponedProcess][Preponed Processes (clocks)]] | Status | Main.JimLewis  | Execute in dedicated delta cycles before normal cycles begin - allows clock propagation - although for simple clock name association &lt;=&gt; will solve the issue | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/122][#122]] | [[AdditionToAllKeywordInSensitivityLists][Process-All and Implicit Signals]] | Status | [[Main.BrentHahoe][Brent Hayhoe]] | Sensitivity = ALL + implicit items: signal'transaction | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/123][#123]] | [[ExtendedStringLiterals][Extended String Literals]] | Status | Main.JimLewis, Main.DanielKho  | Support C Style String Literals | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/92][#92]] | [[TextioBvSlv][Read differences of bit_vector and std_logic_vector]] | Status | Main.JimLewis  | Description | TBD |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/125][#125]] | [[ExternalNon-SharedVariableName][External Non-Shared Variable Name]] | Status | [[Main.BrentHahoe][Brent Hayhoe]] | Add the ability to reference local process variables and VHDL93 shared variables via the 'external name' syntax. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/126][#126]] | [[DeferredSharedVariables][Deferred Shared Variables]]  | Status | Who | Description | [[TopLCS2016_080a][LCS-2016-080a]] %BR% [[TopLCS2016_080b][LCS-2016-080b]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/127][#127]] | [[DeferredSignals][Deferred Signals]] | Status | [[Main.BrentHahoe][Brent Hayhoe]] | Allow deferred signals in packages. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/128][#128]] | Extension to LCS 099 - intended to make more things locally static | Status | Who | Description | [[TopLCS2016_099a][LCS-2016-099a]]  |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/129][#129]] | [[OptionalSemicolon][Extra comma at the end of lists]]  | Status | Who | Description | [[TopLCS2016_071b][LCS-2016-071b]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/130][#130]] | Explore list of system env variables | Status | Who | Need Use Case | [[TopLCS2016_006g][LCS-2016-006g]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/131][#131]] | [[FSMLanguage][Embedded FSM Language]] | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Add a state machine language. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/132][#132]] | [[ReflectionAPICreateValues][Reflection API - Create values]] | RAW | [[Main.LievenLemiengre][Lieven Lemiengre]], [[Main.PatrickLehmann][Patrick Lehmann]] | Create and assign values from mirrors at runtime. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/133][#133]] | [[RelaxedOthersAggregate][Relaxed OTHERS rules in aggregates]] | Status | Main.RyanHinton  | Relax the rules for using OTHERS in array aggregates | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/134][#134]] | [[OverloadAssignment][Overload Assignment Operator]] | Status | Who | Ability to overload the assignment operator := would be useful | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/135][#135]] | Range constructor | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Allow =x downto y= to be used to create a _range record_ instance. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/136][#136]] | [[ExtendedRanges][Extended Ranges]] | Status | Main.PatrickLehmann  | Make ranges more powerful |  [[LCS2016_099][see LCS-2016-099]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/137][#137]] | [[ExtendedUserDefinedAttributes][Extended user-defined attributes]] | Status | Main.PatrickLehmann  | Let users define new attributes, which for example map to functions. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/138][#138]] | [[NewPredefinedAttributeActual][ Subprogram attributes: actual, and formal - use model?]] | Status | [[Main.BrentHahoe][Brent Hayhoe]] | Access subtype information of actual port/parameters | [[TopLCS2016_060][LCS-2016-060]] %BR% [[TopLCS2016_072a][LCS-2016-072a]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/139][#139]] | [[AlternatePathName][Generate Statement Alternate Path Names]]  | Status | Who | Description | [[TopLCS2016_I15][LCS-2016-I15]] . [[TopLCS2016_I15a][LCS-2016-I15a - Dissenting opinion]]  |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/140][#140]] | [[ProcessAllIncudesAllReachableSubprograms][Process(all) sensitivity list Should Not Include Signals in All Reachable Subprograms]] | Status | Who | Description | [[TopLCS2016_I18][LCS-2016-I18]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/141][#141]] | [[WaitRepeat][Wait with a repeat count]] | Status | Main.JimLewis  | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/142][#142]] | [[EnvStop][define parameters for env.stop]] | Status | Who | Define standard parameters for env.stop | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/143][#143]] | [[NamedPkgbody][Named Package Bodies]] | Status | Main.JimLewis | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/144][#144]] | [[UniqueCondition][Unique Condition - OrIf]] | Status | Main.PeterFlake | Description | |
---+++ Integer
| *Repo Issue* | *Proposal* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/145][#145]] | [[ArbitraryIntegers][Integers of arbitrary length]] | Main.MartinThompson  | Add integers of arbitrary length | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/146][#146]] | [[LongIntegers][Long Integers 64 bit type]] | Who | 64 bit integers | [[TopLCS2016_026][LCS-2016-026]] %BR% [[TopLCS2016_026a][LCS-2016-026a]] %BR% [[TopLCS2016_026b][LCS-2016-026b]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/147][#147]] | [[ExtendedIntegers][Extended Integers]] | Main.DanielKho  | Require a minimum of 64 bits for integers. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/148][#148]] | [[EnhancedIntegers][Enhanced Integers]] | Main.JonasBaggett | New derived integer types fittable for synthesis. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/149][#149]] | [[PhysicalTypeRange][Physical Type Range]] | Main.KevinThibedeau  | Require that user-defined physical types can cover the same range as time. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/150][#150]] | [[ModularTypes][Modular Integer Types]] | Main.MartinThompson  | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/151][#151]] | [[ImplicitConversionNumeric][Implicit Conversions for Like Types]] | Who | Addresses issues with assigning integer literals to unsigned, signed, real literals to ufixed, sfixed, and float, and vice-versa. Obviously with some constraints. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/152][#152]] | [[IntegerOperators][Additional Operators to Integers]] | Who | Add Logic Operators for Integers | [[TopLCS2016_051][LCS-2016-051]]  |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/153][#153]] | [[IntegerOperations][Operations on integers]] | Who | Allow boolean and other operations on integers, that have a range as power of two. | |
---+++ Types Enhancements
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/156][#156]] | [[UnionsVariants][Unions and/or Variant Records]] | Status | Main.JimLewis  | Need unions to describe coverage that can either be a range or a single value | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/157][#157]] | [[DiscriminantRecords][Records with discriminants]] | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Create typed unions. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/158][#158]] | [[DerivedIntegerTypes][Derived Scalar types]] | RAW | [[Main.JimLewis][Jim Lewis]], [[Main.PatrickLehmann][Patrick Lehmann]] | Derive integer types (or every scalar type). | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/159][#159]] | [[DerivedEnumerationTypes][Derived enumerations]] | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Derive enumeration types. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/160][#160]] | [[DerivedRecordTypes][Derived records]] | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Derive record types. See tagged records in SUAVE | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/171][#171]] | [[DerivedProtectedTypes][Derived protected types]] | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Derive protected types. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/101][#101]] | [[ExternalNameTypes][Selected names for types]] implementation of external names for types | Status | Who | Description | failed: [[LCS2016_028][LCS-2016-028]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/161][#161]] | [[ExternalNameTypes][Anonymous types for external names]] implementation of external names for types  | 202X partial implemented | Who | Description | failed: [[TopLCS2016_028a][LCS-2016-028a]]  |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/162][#162]] | [[RecordIntrospection][Record Introspection]] | Status | Main.ChrisHiggs  | Convert between a record and a vector | [[LCS2016_041][LCS-2016-041]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/163][#163]] | [[RecordMemberAttribute][Record Introspection & Indexing]] %BR% [[RecordIndexing][Record Indexing]] | Status | [[Main.BrentHahoe][Brent Hayhoe]] | Proposal to allow indexing and scanning of elements within record structures. MERGED (WAS: Member attribute for records) | [[TopLCS2016_069a][LCS-2016-069a]] %BR% [[TopLCS2016_069b][LCS-2016-069b]] |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/164][#164]] | Accessing record elements | RAW | [[Main.BrentHahoe][Brent Hayhoe]], [[Main.PatrickLehmann][Patrick Lehmann]] | Allow handling of records similar to arrays. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/165][#165]] | [[LogicalRepresentationAccess][Access to logical representation of VHDL objects]] | Status | Main.JonasBaggett | Access to binary representation of VHDL objects via new attributes | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/166][#166]] | [[2State][2 and 4 State values]] | Status | Who | Derived / constrained type that automatically and can be controlled during simulation elaboration. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/167][#167]] | [[AliasSubtypePortUnconstrained][Clarify the Subtype of an Alias that refers to an Unconstrained Port]] | Status | Who | Description | |
---+++ Protected Types
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/80][#80]] | Protected Type initialization | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Add a protected type constructor. ?? Already have generics | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/168][#168]] | [[ProtectedTypeWaitSignal][Protected Types with Wait and Private Signals]] | Status | Main.JimLewis  | Description | TBD |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/169][#169]] | [[ProtectedTypesPublicSignal][Protected Types with Public Signals]] | Status | Main.JimLewis  | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/170][#170]] | [[ProtectedTypesCallInDeclartions][Call a method of a protected type in a declaration]] | Status | Main.JimLewis  | Description | |
---+++ Language Regularization
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/172][#172]] | [[ConsistentPackageAPI][Consistent Package API]] | RAW | [[Main.LarsAsplund][Lars Asplund]] | Create a consistent API (mainly naming convention). | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/173][#173]] | [[PackageNameCase][Package Name Case Sensitivity]] | Status | Who | Description | TBD |
---+++ Overhead Tasks
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/174][#174]] | [[BNFCleanup][BNF Clean-up]] | RAW | [[Main.PatrickLehmann][Patrick Lehmann]] | Clean-up BNF rules. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/175][#175]] | [[RequirementNumbers]] - Enumerate 1076 with requirement numbers. | Status | Main.KenCampbell | Description | |
---+++ Testbenches / Continuous Integration
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/176][#176]] | [[ReviewTestbenches][Review testbenches]] | RAW | [[Main.LarsAsplund][Lars Asplund]] and others | Review existing testbenches. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/177][#177]] | [[NewTestbenches][New testbenches]] | RAW | [[Main.LarsAsplund][Lars Asplund]] and others | Add more testbenches. | |
---+++ Packages
| *Repo Issue* | *Proposal* | *Status* | *Who* | *Description* | *TBD* |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/85][#85]] | [[FileIo][DREAD, DWRITE, Integer D, H, O, B Read and Write]]  | Status | NewPerson | Description | [[TopLCS2016_006b][LCS-2016-006b]]  |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/178][#178]] | [[SubsumeIEEE10764][Subsume IEEE Std. 1076.4]] | RAW | [[Main.JimLewis][Jim Lewis]], [[Main.PatrickLehmann][Patrick Lehmann]] | Reactivate IEEE Std. 1076.4 Timing (VITAL) as part of IEEE Std. 1076. | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/179][#179]] | [[StandardPackages][Updates to standard packages - split into LRM and Packages]] | Status | Main.RyanHinton  | Additions to LRM, standard, std_logic_1164, numeric_std, math_real, math_complex, and fixed_pkg. Some may be redundant | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/180][#180]] | [[MoveText][Move definition of TEXT, INPUT, OUTPUT]] | Status | Who | <p>Could have a context declaration that does:</p> <p>Context IO is</p> <p>use std.textio.text ;</p> <p>use std.textio.OUTPUT;</p> <p>use std.textio.INPUT;</p> <p>end context;</p> | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/181][#181]] | [[StopReadOnTrailingUnderscore][Stop Binary/Octal/Hex Read At Trailing Underscore]] | Status | Main.CliffordWalinsky  | [[https://gitlab.com/IEEE-P1076/Packages/issues/24][Test results from GitLab]] LRM already does this. Could be better written, but is correct and tests correct in simulations | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/182][#182]] | [[MetavalueConditionalConversions][Flag metavalues detected by ??]] | Status | Main.JimLewis  | Description | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/183][#183]] | [[RealMatrixPackage][Real Matrix Math Package (and Vector)]] | Status | Main.DavidBishop | [[http://www.vhdl.org/fphdl/real_matrix_ug.pdf][Matrix Math User's Guide (pdf)]] %BR% [[http://www.vhdl.org/fphdl/real_matrix_pkg.zip][Packages (zip)]] | |
| | [[StandardPackages][Updates to standard packages - split into LRM and Packages]] | Status | Main.RyanHinton  | <p>Note this is listed here and in enhancements.</p> <p>Additions to LRM, standard, std_logic_1164, numeric_std, %BR% math_real, math_complex, and fixed_pkg</p> | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/184][#184]] | [[NaturalVector][Create natural_vector]] | Status | Main.JimLewis  | Create natural_vector as a subtype of integer_vector  | |
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/185][#185]] | [[UpdateStdLogicArith][Update std_logic_arith]] | Status | Main.JimLewis  | Update std_logic_arith to simplify interoperability with numeric_std | |

---+++ VHDL AMS 1076.1 Proposals that go in 1076
| *Item*  | *Who*  | *Status*  | *Last Modified* | *Description*  | *Status* |
| Table Driven Modeling | Joachim Haase et.al.  | %LIMEBG%Forwarded to Open Source Group%ENDBG% | 5/24/2012 | The package supports the description of functional dependencies y = f(x<sub>1</sub>, x<sub>2</sub>, ..., x<sub>n</sub>) based on a number of (n+1)-tupels (y, x<sub>1</sub>, x<sub>2</sub>, ..., x<sub>n</sub>). Emphasis is on floating point functions, and various interpolation schemes are supported. More details, and a reference implementation can be found in a [[P10761.ProjectTableDrivenModeling][protected area]] of the P1076.1 web. | 202X |

---+++ Change Proposals for IEEE Packages
| *Item* | *Who*  | *Status*  | *LCS Link*  | *Rank*  | *Description*  | *Final Status* |
| [[FixedFloatUpdates][numeric_std, fixed and float bugs and consistency updates]] | Main.DavidBishop | | | 3  | Bug fixes and consistency updates for numeric_std, %BR% fixed_generic_pkg.vhd, and float_generic_pkg.vhd | Ask David |
| [[http://www.vhdl.org/fphdl/fixed_alg_ug.pdf][Fixed point Algorithmic User's Guide (pdf)]] | Main.DavidBishop | REVIEW  | | | [[http://www.vhdl.org/fphdl/fixed_alg_pkg.zip][Package (zip)]]  | Open Source Doc |
| [[http://www.vhdl.org/fphdl/float_alg_ug.pdf][Floating point Algorithmic User's Guide (pdf)]] | Main.DavidBishop | REVIEW  | | | [[http://www.vhdl.org/fphdl/float_alg_pkg.zip][Package (zip)]]  | Open Source Doc |

---++ Someday Maybe Proposals
| *Repo Issue* | *Item* | *Who*  | *Status*  | *Rank* | *Description*  | *Status* ||
| | [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals/VHDL-2005-VHPI-impact.pdf][VHPI Impact]] | | | | VHDL-2008 & VHDL-2019 impact to VHPI | Low Priority ||
| | [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/proposals/vhpiPSLassertion.pdf][VHPI for PSL]] | | | | PSL impact to VHPI | Low ||
| | [[FloatInstance][Standard Instances of Float]] | OPEN | | | Define standard instances of float_generic_pkg and fixed_generic_pkg | Low ||
| | [[VectorLiteralntrospection][Vector literal introspection]] | Main.JimLewis  | RFC  | 35  | Distinguish between std_logic_vector and integer_vector literals  | Low ||
| | [[ObjectOrientation][Object Orientation]] | | | 39  | Links to different proposals  | Low ||
| | [[ArchitectureGeneric][Architecture Generic]] | Main.LarsJensen  | RFC  | 83  | Implements architecture instantiation through generics | Low ||
| | [[DynamicProcessInstance][Dynamic Process, Instances, Fork Join]] | | | 91  | | Low ||
| | [[ShorthandSubprogram][Shorthand Subprogram Declarations]] | Main.JimLewis  | -  | 92  | -  | Low ||
| | [[TruthTable][Truth Tables]] | Need Owner  | | 98  | Truth table for multi-input/multi-output  | Low ||
| | [[Asynchronous Channels]] | Main.KevinCameron  | | 100 | Asynchronous channels (aka pipes)  | Low ||
| [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/76][#76]] | [[ClockedShorthand][Clocked Shorthand]] | Main.DanielKho  | RFC  | 103 | <p>Shorthand to infer flip-flops and pipelining</p> <p>Z &lt;= A when rising_edge(Clk) ;</p> <p>process(A, Clk)</p> <p>begin</p> <p>if rising_edge(Clk) then</p> <p>Z &lt;= A ;</p> <p>end if ;</p> <p>end process ;</p> <p>Z &lt;= A when Sel = '1' else B ;</p> | Open Source Group? ||
| | [[DynamicRewiring][Dynamic Rewiring]] | Main.KevinCameron  | | 105 | Allow runtime re-elaboration and re-wiring  | ||
| | [[AttributeShorthand][Attribute Shorthand]] | Main.DanielKho  | RAW  | | Shorthand to create attributes.  | ||

---++ Rejected Proposals
| *Item*  | *Who*  | *Status*  | *Rank* | *Description*  | *StatusPriority* ||
| [[Object Inspection]]  | Main.JingPang | RAW | | Method to do introspection on names, find different objects and find all instance labels whose component is xyz. | see VHPI ||
| [[UseOfUnicode][Use of Unicode]] | Main.MartinThompson | Reject | | Add unicode for strings, files, identifiers, comments | 202X - Issue, UFT8 - How do we size strings - one character may require multiple multiple UTF8 characters. Current scope prevents multibyte issues. See python 3 when switched to unicode. |

---++ Items Subsumed by other items
| *Item* | *Who* | *Status* | *Description* | *Supporters Priority* |||
| [[SignalPools][Signal Pools]] | Main.KevinCameron | | | Ranking: 106 - Alternative to wire-like communication for RF | ||
| [[UserDefIOrules][User Defined IO Rules]] | Main.KevinCameron | | | Ranking: 107 - Move rules about in/out/inout to types | ||
| [[ProtectedTypeUpdates][Protected Type Updates]] | Main.JimLewis | - | | Numerous | ||

---++ Proposals for 1076.6 - Requires a Chair for this activity

Requires separate working group and vendor participation.

This work would potentially be done by a separate working group. Requires a chair. Main.JimLewis will help you through the IEEE process, but you will need to get vendor participation for the effort to be relevant.

| *Item*  | *Who*  | *Status*  | *Last Modified* | *Description*  | *Supporters Priority* |
| [[FSMSafeDesign][FSM Safe Design]] | [[Main.BrentHahoe][Brent Hayhoe]] | RFC | | Proposal to allow safe state identification for synthesis in FSM designs. | |
| [[SynthesisAttributes][Synthesis Attributes]] | | | | Attributes for RAM, ROM, ... Define these in 1076? | |
| [[AssertionDirectives][Assertions as Directives]] | main.JimLewis | | | Support ZeroOneHot, ... | |
| [[SupportReal]] | | | | | |
| [[SynthesizableEvent][Synthesizable 'event]] | | | | | |
| [[SupportReal][Support Synthesis of Reals]] | Main.DanielKho  | RAW  | | Simplify synthesis of floating-point operations, by using real to encapsulate synthesizable fixed- or floating-point types. | Synthesis ||
| [[SynthesizableReportsAssertions][Synthesizable Reports and Assertions]] | Main.DanielKho | RFC | 77 | <p>Allow assertions to count in synthesis</p> <p>Emulator behavior</p> <p>Reporting to the synthesis log? Check generic values are appropriate?</p> <p>Compile time assertions?</p> | Synthesis ||
| [[MultiCyclePath][Multicycle Path Specification]] | | | 97 | Speciification of multi-cycle paths in language syntax | Synthesis ||
| [[TimingConstraints][Specifying Timing Constraints]] | Main.DanielKho | RAW | | Allows RTL designers to specify timing constraints directly from HDL. | Synthesis ||
| [[SynthesizableEvent][Synthesizable 'event Attribute]] | Main.DanielKho | RAW | | Synthesize 'event for DDR FFs. | Synthesis ||
| | | | | | |

---++ Items to forward to open source package group
| *Item* | *Who* | *Status* | *Last Modified* | *Description* | *Supporters Priority* |
| [[ReadRom][File IO for RTL ROM]] | Main.JimLewis | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | Ranking: 24 - File IO for RTL ROM | ||
| [[FunctionalCoverage][Functional Coverage]] | Main.JimLewis | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | Implemented by open source group [[http://www.osvvm.org][OSVVM]] | |
| [[RandomStimulus][Random Stimulus]] | Main.JimLewis | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | Implemented by open source group [[http://www.osvvm.org][OSVVM]] | |
| [[SemaphoreDataStructure][Semaphores]] | | | | | |
| [[ExtendedHwFunctions][Extended Hardware Functions - RTL Macros]] | | %LIMEBG%Forwarded to Open Source Group%ENDBG%  | | RTL Macros. Meeting: [[MeetingDecember15][Dec 15, 2011]] and [[MeetingMarch31][Mar 31, 2011]] | |
| Associative Arrays | | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | See [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-tbv/vhdl-200x-tbv.pdf][TBV Propoal 2]] | |
| Queues / FIFO | | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | See [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-tbv/vhdl-200x-tbv.pdf][TBV Proposal 4]] | |
| Sync and Handshaking | | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | See [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-tbv/vhdl-200x-tbv.pdf][TBV Proposal 7]] | |
| Memory / Sparse array | | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | See [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-tbv/vhdl-200x-tbv.pdf][TBV Proposal 12]] | |
| Loading and Dumping Memories | | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | See [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-tbv/vhdl-200x-tbv.pdf][TBV Proposal 18]] | |
| Lists | | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | See [[http://www.eda-twiki.org/vhdl-200x/vhdl-200x-tbv/vhdl-200x-tbv.pdf][TBV Proposal 19]] | |
| Create open source boost/C++ like libraries | | | | Meeting: [[MeetingDecember15][Dec 15, 2011]] | |
| [[IntegerConv][to_integer and to_integer_vector]] | Main.JimLewis | - | | - | |
| [[GraphicsLibrary][Graphics Library]] | Main.DanielKho | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | Implement a graphics library for VHDL. | ||
| [[RegularExpressions][Regular Expressions]] | Main.DanielKho | %LIMEBG%Forwarded to Open Source Group%ENDBG% | | Implement VHDL regular expressions. | ||
| | | | | | |

---++ Raw Requirements Lists
| *List* | *Description* | *Notes* |
| [[http://www.eda-twiki.org/twiki/bin/view.cgi/P1076/Vhdl2019ActiveIRTwiki][ISAC Active IR List]]  | | |
| [[Vhdl2019ActionItems][Old Meeting Action Item List]]  | Current Action Items now tracked in meeting minutes | |
| [[https://bugzilla.mentor.com/buglist.cgi?query_format=specific&order=relevance+desc&bug_status=__all__&product=&content=][Bugzilla List]]  | | |
| [[IeeeVHDL2008Lists][IEEE VHDL 2008 Subgroup Lists (TBV, FT, DTA, )]] | | |
| [[AccelleraVHDL2008Lists][Accellera VHDL 2008 Remaining Items List]] | | |
| [[RawRequirements][Raw Requirements in Text of Original Page]] | | |

   * [[%ATTACHURL%/vhdl_requirements_priority.xlsx][vhdl_requirements_priority.xlsx]]: VHDL Requirements Prioritization Sheet

   * [[%ATTACHURL%/TbIntegerRange.vhd][TbIntegerRange.vhd]]: IntegerRanges and expressions - where do the bounds apply
Topic revision: r25 - 2021-05-16 - 16:02:22 - UnaiCorral
P1076