API and Attributes for PSL

Proposal Editing Information

  • Who Updates:
  • Date Proposed: 2020-June-4
  • Date Last Updated:
  • Priority:
  • Complexity:
  • Focus: Testbench
  • Proposal Maturity:

Requirement Summary

In VHDL, it is allowed to leave an output port of a component open. Is there a function to detect that from within the component so that other hardware could be generated?

I don't want to wait on the optimisation step, since I would like to modify the hardware in case a port is left open.

Specifically, I'm generating a component with differential output, in which I would like to include a OBUFDS in case both _P and _N are connected, and I don't want to include that component in case the _N is left open.

Rationale

Related and/or Competing Issues:

Proposal

Attribute Determined at Elaboration Time

CreateDriver : if Sig_N'Driven generate -- Attribute name up for discussion, Driven, Undriven, 

  ... -- instantiate a differential driver

else

  ... -- instantiate a single driver to drive Sig_P only

end generate CreateDriver ;

Also need to be able to do Sig.N'Driven where sig is:

type SigType is record
  N : std_logic ;
  P : std_logic ; 
end record SigType ; 

Questions

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Topic revision: r2 - 2020-07-02 - 19:11:12 - JimLewis
 
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