Protected Types with Public Signals

• Who Updates: JimLewis, <Add YourName >, ...
• Date Proposed: 2012-Jan-05
• Date Last Updated: 2014-Nov-13 (split out from ProtectedTypeUpdates)
• Priority:
• Complexity:
• Focus: Testbench

Requirement Summary

Allow public signals in a protected type declarative region. Access to these signals shall use a record like dot notation. Values driven from within the protected type are deposit only (similar to private Signal/Event class objects). Values driven from outside the protected type have normal drivers.

Allows protected type to be an abstract communication channel with similar capabilities to an interface in SystemVerilog.

Questions

General Comments

-- ErnstChristen - 2015-01-27

There are about 6 proposals related to improving the management of ports:

• Records with Directional Subtypes
• Packages as an interface construct
• Interface Construct and Port Mode Configurations
• Add "Bus" mode for bidirectional port signals
• Protected Types with Public Signals - This proposal
• Protected Type on Entity Interface

It would be worthwhile to derive generic requirements for port/interface management instead of looking at them in isolation.

Supporters

Add your signature here to indicate your support for the proposal

-- JimLewis - 2014-12-03

-- Brent Hayhoe - 2014-12-22

-- MortenZilmer - 2015-01-21

-- PatrickLehmann - 2016-02-19