P1076 Web>VHDLProposals>DerivedRecordTypes (2017-04-02, PatrickLehmann)EditAttach

Derived Record Types

Proposal Details

Authors	Patrick Lehmann
Date Proposed	2017-04-03
Last Updated	2017-04-03
Focus	simulation and synthesis
LCS	TBD

Summary
Current Situation
Requirement
Use Cases
Implementation details
Code Examples
Arguments FOR
Arguments AGAINST
General Comments
Supporters

Summary

VHDL-2017 introduced mode views based on records. Composing large buses like AMBA4 - AXI Lite is done by nesting multiple records. While this works well for the AXI Lite example, it has some drawbacks for conventional on-chip buses like AMBA4 AXI Stream. This bus is defined as a base bus with optional wires. Using nested records to model such a bus creates a deep data structure, whereas the original bus model is a flat structure.

Derived record types allows to extend an existing record type with additional elements, without creating a deeper data structure.

Current Situation

Describe the current situation in this section.

Requirement

Features:

Extend a record type with new elements.
Create implicitly defined conversion functions for these types.

Use Cases

AMBA4 - AXI Stream
Xilinx LocalLink
PoC.Stream

Implementation details

How is it implemented?

Code Examples

-- a basic FIFO-like streaming bus with bidirectional handshake
type BaseBus is record
  Valid : std_logic;
  Data  : std_logic_vector;
  Ack   : std_logic;
end record;

-- an extended streaming bus with frame information
type FramedBus is new BaseBus is record
  StartOfFrame : std_logic;
  EndOfFrame   : std_logic;
end record;
--type BaseBus is record
--  Valid        : std_logic;
--  Data         : std_logic_vector;
--  Ack          : std_logic;
--  StartOfFrame : std_logic;
--  EndOfFrame   : std_logic;
--end record;

-- an extended framed bus with payload information
type FramedBusWPayload is new FramedBus is record
  StartOfPayload : std_logic;
  EndOfPayload   : std_logic;
end record;
--type BaseBus is record
--  Valid          : std_logic;
--  Data           : std_logic_vector;
--  Ack            : std_logic;
--  StartOfFrame   : std_logic;
--  EndOfFrame     : std_logic;
--  StartOfPayload : std_logic;
--  EndOfPayload   : std_logic;
--end record;

Arguments FOR

Arguments AGAINST

General Comments

Supporters

Patrick Lehmann
Add your signature here to indicate your support for the proposal

Topic revision: r1 - 2017-04-02 - 22:39:25 - PatrickLehmann

P1076