Who am I?

After a basic education in computer science, I specialized in computer engineering, especially in FPGA designing with
Xilinx ISE, Xilinx Vivado and Altera Quartus-II as well in simulation and verification of such implemented designs.
While studding in the master program, I got involved in giving lectures and labs on hardware design, too.

My first big project was a streaming optimized controller for the Serial-ATA protocol. One major goal of this controller
was to be platform independent in means of FPGA device, FPGA family, FPGA vendor and even tool chain vendor
independability. The second project was a Gigabit-Ethernet stack for UDP/IPv4/IPv6, which had the same goals as before.

My major commitment now focuses on streaming optimized and platform independent hardware modules, which are
provided open source on GitHub, named PoC -Library. A second commitment is my PicoBlaze -Library, an extension to
the PicoBlaze processor written by Ken Chapman. This library provides a System-on-Chip ecosystem for the PicoBlaze.

My Links

• The PoC-Library - an open source, vendor and plattform independent VHDL IP core library
• The PicoBlaze-Library - a System-on-FPGA ecosystem for the PicoBlaze 8-bit CPU
• JSON-for-VHDL - bringing VHDL tools to the edge by parsing JSON files in VHDL

Proposals for the next VHDL revision (VHDL-2020):

• Drived Types
  • Derived integer types (all scalar types?)
  • Derived enumerations
  • Derived records
  • Derived protected types
• Records with discriminants
• Reflection API
  • Create and assign values at runtime
• Accessing Record elements (LCS 069)
• Map functions
• Signal map aspect (LCS 070a)
• Operations on integers (power of 2 integers)
• User defined attributes
• Deferred
  • Shared Variables
  • Signals
• Selectable Architecture
• Protected type initialization
• Allow work in context
• Hierachical names
• Slice multi dimensional arrays
• Create range shorthand
• State machine language

old

• Extended Ranges
• Extended User Defined Attributes
• Attribute Propagation Rules

LCS written for VHDL-2017:

1. Improved file API
2. Improved directory API
3. Sequential deklarative regions - for if, case, loop statements
4. Allow Access Types to Protected Types and Composites of Protected Types
5. Report Calling Path
6. New attributes for scalar types
7. New attributes - ='index=
8. New attributes - ='designated_subtype=
9. Garbage Collection
10. Reflection API
11. Interface Construct and Port Mode Configurations
12. Interface Construct and Port Mode Configurations - ='converse=
13. API for Assert
14. Improved Type Generics
15. Ordering of any scalar array type
16. Bidirectional Connections
17. Function Knows Vektor Size
18. Extended Ranges
19. ISAC 03 - Signatures Required in Association Lists
20. Updating reference IEEE Standards

Delayed

Rejected

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• Reflection for VHDL
  

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