Results from P1076/Ballots web retrieved at 15:19 (GMT)
Define 2 4 State Semantics for std ulogic Recommendation: Investigate Further Proposal Information Who Updates: Date Last Updated Priority:...
Abstract Packages Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 17 Date Last Updated: 2012 08...
Accellera TC Remaining Items Item Description Tracking / Proposal Reviewed On Supporters Priority Requirements List from VHDL 2008...
Active IR List from VHDL 2008 Revised: JimLewis 2014 06 22 IRs accepted for consideration in VHDL 201X These items have been forwarded from ISAC requests to be...
Additional Interface Related Proposals Interfaces: Attributes for Interfaces provides new attributes to shortcut support for new interface modport construct...
The bugzilla report 293 states that it is unclear whether the alternative label possible in an if or case generate statement forms part of the path name. The proposed...
Anonymous Types on Interfaces Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 18 Date Last Updated:...
Architecture Generic Proposal Details Who Updates: LarsJensen Date Proposed: 2013 02 15 Date Last Updated: 2013 02 15 Priority: Complexity...
Array Type Generics Proposal Information Who Updates: RyanHinton Date Proposed: 2013 05 02 Date Last Updated: 2013 05 02 Priority: Complexity...
API for VHDL Assert Statements Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 17 Date Last Updated...
Assertions as Directives Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2014 04 30 Date Last Updated:...
Signatures Required in Association Lists Proposal Details Who Updates: CliffordWalinsky , JimLewis, RyanHinton Date Proposed:December 20, 2012 Date...
Asynchronous Data Channels Proposal Details Who Updates:Main.KevinCameron Date Proposed: Date Last Updated: Priority: Complexity: Focus...
Atomic Composite Signals Recommendation: Investigate Further Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus...
Attribute Shorthand Proposal Details Who Updates: DanielKho, Add YourName Date Proposed: Date Last Updated: Priority: Complexity:...
Requirement Name Proposal Details Who Updates: TristanGingold Date Proposed:2014 12 30 Date Last Updated: Priority: Complexity: Focus...
Records with Directional Subtypes Proposal Information Who Updates: PeterFlake, ... Date Proposed: 2012 06 22 Date Last Updated: 2012 06 22 Priority...
Simple record based interface One reason that the interface proposal was initially put forward: engineers want to put their structural level signal interconnects...
Bundles in VHDL Introduction This page discusses issues around defining the concept of a bundle in VHDL. We use the term bundle here instead of interface to distinguish...
Bundles Proposal Details Who Updates: LievenLemiengre Date Proposed: 2016 04 12 Date Last Updated: 2016 04 12 Priority: high Complexity:...
Requirement Name Proposal Details Who Updates: Date Proposed:2014 10 17 Date Last Updated: Priority: Complexity:Easy Focus: Current...
Clocked Shorthand Proposal Details Who Updates: DanielKho, JimLewis, ... Date Proposed: 4 Jan 2012 Date Last Updated: 4 Jan 2011 Priority:...
Zero delay ordering of Clocks vs. Data signals Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity...
P1076 Proposals and Requirements When you add a new page to this twiki that is intended to have all the details for a new requirement, there is a template you may...
Component Declaration Derived from an Entity Declaration Proposal Editing Information Who Updates: Open Transcribed by: JimLewis Date Proposed:...
Composing Paths to External Names Proposal Details Who Updates: Date Proposed: Date Last Updated: Priority: Complexity: Focus: Requirement...
Conditional Compilation Proposal Details Who Updates: JohnShields, ... Date Proposed: 8/15/2011 Date Last Updated: 9/21/2011 Priority: Complexity...
Configure Direct Instantiation IN PROGRESS! Proposal Information Current Owner: RyanHinton Contributors: RyanHinton, JimLewis, AndyJones, DanielKho...
Functional Coverage and Randomization Proposal Information Who Updates: JimLewis, ... Date Proposed: 2011 07 16 Date Last Updated: 2011 07 16...
Foreign / Cross Language Model Instances Proposal Editing Information Who Updates: . Date Proposed: Date Last Updated: Priority: Complexity...
Candidate 1: Bundles specified as a type definition Think of a bundle as being an enhanced version of a record. A bundle uses the concept of conjugated modes, while...
Subprograms ## Single syntax for functions and procedures to do without declaration and definition regions. E.g.: package subs is end package subs; package body subs...
Date and Time Proposal Editing Information Who Updates: MortenZilmer, Add YourName , ... Date Proposed: 2012 08 19 Date Last Updated: 2013 11...
Deferred Shared Variables Proposal Details Who Updates: BrentHayhoe, JimLewis Date Proposed: 2012 12 16 Date Last Updated: 2013 01 29 BrentHayhoe...
Direct Programming Interface Proposal Details Who Updates: PeterFlake Date Proposed: Date Last Updated: Priority: Complexity: Focus...
Dynamic Process, Instances, Fork and Join Proposal Information Current Owner: ... Contributors: ... Date Proposed: 2014 June 22 Date Last Updated...
Dynamic Connectivity Proposal Details Who Updates: KevinCameron Date Proposed: Date Last Updated: Priority: Complexity: Focus: Current...
Encryption Updates Proposal Editing Information Who Updates: JarekKaczynski, JohnShields Date Proposed: Date Last Updated: Priority: Complexity...
Define Entity Classes of 2008 Related Declarations in Attribute Specifications Proposal Details Who Updates: main.CliffordWalinsky , Date Proposed:January...
Enhanced integers Proposal Details Who Updates: JonasBaggett Date Proposed: 2016 07 30 Date Last Updated: 2016 08 02 Priority: Complexity...
Attributes for Enumerated Types Proposal Editing Information Who Updates: JimLewis, PatrickLehmann, Add YourName , ... Date Proposed: 2012 08 17 Date...
Standard Parameters for Std.Env.Stop Proposal Information Who Updates: JimLewis, Needs Champion Date Proposed: 2014 03 23 Date Last Updated: 2014...
Expressions In Sensitivity List Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus:...
Expressions in Bit String Literals Proposal Editing Information Who Updates: Brent Hayhoe, DavidKoontz, DanielKho, Add YourName , ... Date Proposed:...
Extended Hardware functions like mux, decoders, adders Proposal Editing Information Who Updates: Date Proposed: Date Last Updated: Priority:...
Require 64 bit Integers Proposal Details Who Updates: Date Proposed: Date Last Updated: Priority: Complexity: Focus: Related Issues...
Extended Ranges Proposal Editing Information Who Updates: Patrick Lehmann, Lieven Lemiengre, Add YourName , ... Date Proposed: 2016 07 19 Date...
Extended String Literals Proposal Details Who Updates: JimLewis Date Proposed: Date Last Updated: Priority: Complexity: Focus: Requirement...
Extended User Defined Attributes Proposal Editing Information Who Updates: PatrickLehmann, Add YourName , ... Date Proposed: 2016 07 19 Date Last...
External Names for Types Proposal Information Current Owner: JimLewis, ... Contributors: JimLewis, ... Date Proposed: 2014 May 26 Date Last Updated...
External Non Shared Variable Name Proposal Editing Information Who Updates: Brent Hayhoe Date Proposed: 2014 08 11 Date Last Updated: Priority...
FSM Safe Design Proposal Details Who Updates: Brent Hayhoe Date Proposed: 2014 02 24 Date Last Updated: Priority: Complexity: Focus...
File IO / Textio updates Proposal Editing Information Who Updates: JimLewis, , ... Date Proposed: 2012 08 18 Date Last Updated: 2013 09 20 Priority...
Repair Text on Context Clauses Proposal Details Who Updates: DanielKho, CliffordWalinsky Date Proposed:2013 12 09 Date Last Updated:2013 12 09...
Repair LRM Example 7.3.2.1 Proposal Details Who Updates: DanielKho Date Proposed: Date Last Updated: Priority: Complexity: Focus: Current...
Repair Generate Statements Proposal Details Who Updates: TristanGingold Date Proposed: 2015 01 10 Date Last Updated: Priority: Complexity...
Bug fixes and consistency updates to numeric std, fixed generic pkg, and float generic pkg. Proposal Information Who Updates: DavidBishop, JimLewis, TristanGingold...
Additional standard instances for fixed generic pkg and float generic pkg Proposal Information Who Updates: JimLewis, Needs Champion Date Proposed:...
Forcing Outports Issue Information Reporter: John Shields via VHDL 200X reflector Contributors: Jim Lewis, ... Date Proposed: 2012 January 4 Date...
Method to allow functions to know the output vector size (ISAC IR2132, Bugzilla #240) Proposal Details Who Updates: Kevin Jennings Date Proposed: Sep...
Functional Coverage Proposal Information Who Updates: JimLewis, ... Date Proposed: 2011 07 16 Date Last Updated: 2012 11 29 Priority: Complexity...
WithDrawn: Functions Know Output Subtype Proposal Information Who Updates: Date Proposed: April 4, 2013 twiki Date Last Updated: 27 Feb 2014 Priority...
Garbage Collection Proposal Editing Information Who Updates: JimLewis, CliffordWalinsky, Add DavidKoontz 2014 09 25 , ... Date Proposed: 2013 04...
Issues with Generic Mapped package Proposal Details Who Updates: Date Proposed:2016 09 15 Date Last Updated: Priority: Complexity:Low...
Generics on Protected Types Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 17 Date Last Updated:...
Graphics Library Proposal Details Who Updates: DanielKho, Add YourName Date Proposed: 2015 01 03 Date Last Updated: Priority: Complexity...
Heterogeneous Interfaces Ernst Christen, Mentor Graphics 1. Introduction As part of the work on P1076 201x, several proposals have been made that aim at providing...
Heterogeneous Interfaces in VHDL Proposal information Who Updates: ErnstChristen, ... Date Proposed: 2015 03 05 Date Last Updated: 2015 11 05...
Heterogeneous Interfaces with Emphasis on Compactness Proposal information Who Updates: ErnstChristen, ... Date Proposed: Date Last Updated:...
Heterogeneous Interfaces with Emphasis on Reusing Existing VHDL Concepts Proposal Details Who Updates: ErnstChristen Date Proposed: 2015 11 05 Date...
Hierarchical Libraries Proposal Details Current Situation Packages and entities may be compiled into libraries. The library hierarchy is flat, ie. libraries cannot...
P1735 Visibility model Proposal Details Who Updates: StevenDovich Date Proposed: Date Last Updated: Priority: Complexity: Focus: Current...
VHDL 2008 TBV Review Item Description Tracking / Proposal Reviewed On Supporters Priority Proposals Vhdl2019ActionItems TBV...
Implicit Numeric Conversions Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2014 10 14 Date Last Updated:...
Integer and Integer vector conversions Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 19 Date Last...
Interface and Bundle Requirements Accepted Requirements (draft) The interface construct was originally prompted by the requirement for better support in order...
Attributes for interfaces JohnAasen 2015 03 19 Proposal Details Who Updates: JohnAasen Date Proposed: 2015 03 19 Date Last Updated:2015 03 19...
Interface Bundle Requirements Interfaces were originally conceived as using the standard record type to group various signal types together. A VHDL AMS...
New Interface Port/Parameter Mode Requirements From an RTL perspective... A new `interface` construct with a primary aim to capture customized mode structures...
Interface Semantics Discussion Interface construction within VHDL is largely supported by composite types, which include array types and record types. These allow...
Interface Discussions Pages for the bullet points and questions relating to various aspects of the proposed new Interface construct. Heterogeneous Interface Requirements...
Issue Screening and Analysis Committee (ISAC) Mission The ISAC subcommittee analyzes reports of errors and ambiguities in the standard, as well as requests for enhancement...
Scope of Keywords Proposal Details Who Updates: JimLewis Date Proposed:30 Mar 2014 Date Last Updated: 30 Mar 2014 Priority: Low Complexity...
Typographical Issues in IEEE Std 1076 2008 This is a collection of typographical issues in the LRM that are not captured by their own pages. Section 6.5.2 Interface...
Issue Screening and Analysis Committee (ISAC) Language Clarification Proposals These proposals are intended to clarify current language features that have clarification...
Light Weight Signals Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus: Performance...
Support C like macros Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus: Performance...
Map Subprogram Generics on call Proposal Editing Information Who Updates: OPEN, JimLewis Date Proposed: 2012 08 17 Date Last Updated: 2012 08 17...
P1076 December 1, 2011 Meeting Minutes Unapproved Attendees: To be held Agenda: To be held Whiteboard for Current Agenda Topic 1 stuff Topic...
JimLewis 2011 03 16 March 17, 2011 Meeting Minutes
P1076 MMMM DD, YYYY Meeting Minutes Attendees: attendees Agenda: Meeting Discussion What`s Next see PrivateDocuments file: summary vhdl requirements...
P1076 November 25, 2011 Meeting Minutes Unapproved Attendees: To be held Agenda: To be held Whiteboard for Current Agenda Topic 1 stuff Topic...
Flag Metavalues detected by ?? Proposal Information Current Owner: JimLewis, ... Contributors: JimLewis, ... Date Proposed: 2014 October 16 Date...
Mixed Signal Support Proposal Information Who Updates: KevinCameron, ... Date Proposed: Date Last Updated: Priority: Complexity:medium...
Move std.textio.TEXT, OUTPUT, and INPUT Proposal Information Who Updates: JimLewis, Needs Champion Date Proposed: 2014 03 23 Date Last Updated:...
Status Quo and Moving Forward with Bundles Ernst Christen, Mentor Graphics The Status Quo Since its first version in 1987, VHDL has supported design entities with...
Multicycle Path Proposal Information Current Owner: None, ... Contributors: None, ... Date Proposed: 2014 June 22 Date Last Updated: 2014 June...
Multiple Design Hierarchies Proposal Details Discussed on: 2016 MeetingJune2 Need clear explanation of use model and someone to work on it....
Named Package Bodies Proposal Editing Information Who Updates: JimLewis, DavidBishop, Add YourName , ... Date Proposed: 2012 08 20 Date Last Updated...
natural vector Proposal Information Who Updates: OPEN Date Proposed: 2014 03 23 Date Last Updated: 2014 03 23 Priority: Complexity:...
Create New LCS New LCS name WGNAME WGFORMNAME WGTEMPLATENAME LCSNUMBER...
New Predefined Attributes: `actual, and `formal Proposal Editing Information Who Updates: Brent Hayhoe Date Proposed: 2014 07 14 Date Last Updated...
Additional Rules for Bit String Literals Proposal Details Who Updates: DanielKho Date Proposed: Date Last Updated: Priority: Complexity:...
User Defined Attributes May Not Redefine Predefined Attributes Proposal Details Who Updates: CliffordWalinsky Date Proposed:2013 12 9 Date Last Updated...
Object Introspection in VHDL Proposal Details Who Updates: Jing Pang Date Proposed: 2015 7 15 Date Last Updated: 2015 7 15 Priority: Complexity...
Object Introspection in VHDL Proposal Details Who Updates: Jing Pang Date Proposed: 2015 7 15 Date Last Updated: 2015 7 15 Priority: Complexity...
Object Orientation Proposal Information Current Owner: ... Contributors: ... Date Proposed: 2014 June 22 Date Last Updated: 2014 June 22...
All Interface Lists Can Be Ordered Proposal Details Who Updates:Main.CliffordWalinsky Date Proposed:2013 11 12 Date Last Updated:2013 11 12 Current...
Overload Assignment `: ` Proposal Information Who Updates: JimLewis, Needs Champion Date Proposed: 2013 10 11 Date Last Updated: 2013 10 31 Priority...
Overloaded Assignments Proposal Details Who Updates: AndyJones Date Proposed: 2013 05 03 Date Last Updated: Priority: Complexity: Focus...
Package Updates for VHDL 2017 Proposal Information Who Updates: DavidBishop, JimLewis, ... Date Proposed: 2016 05 19 Date Last Updated: 2016...
PATH NAME and INSTANCE NAME for Protected Types and Subprograms Proposal Information State of this Proposal: Current Owner: JimLewis, ... Contributors...
Physical Type Ranges Proposal Details Who Updates: KevinThibedeau, Add YourName Date Proposed: 2015 1 15 Date Last Updated: Priority:...
Placeholder page for this proposal For now you can take a look at the attachments I quickly hacked the modifications into our compiler both files already pass syntax...
package util is type logger is protected procedure log(msg : string; sev : severity level); end protected; end package; library ieee; use ieee.std logic...
Precedence of Unary Logical Operators Proposal Information Who Updates: JimLewis, , ... Date Proposed: 2013 11 14 Date Last Updated: 2013 11 14...
Preponed Processes Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 19 Date Last Updated: 2012 08...
Hi David, I can try and motivate the include concept first, and then open the can and look into that. You aren t the first to ask why we need it, but so far I felt...
The Sensitivity List for Process(all) Should Not Include Signals in All Reachable Subprograms Proposal Details Who Updates:main.CliffordWalinsky Date Proposed...
Composition with Protected Types Proposal Information State of this Proposal: Raw / Stream of Conscious Current Owner: JimLewis, ... Contributors:...
Protected Type: Shared Variables On Entity Interface Proposal Information State of this Proposal: Current Owner: JimLewis, ... Contributors: JimLewis...
Operator Overloading for Protected Types Proposal Editing Information Who Updates: Add YourName , ... Date Proposed: Date Last Updated: Priority...
Depricated: Protected Type Update Now separate proposals Proposal Information State of this Proposal: Raw / Stream of Conscious Current Owner: JimLewis...
Protected Types: Wait and Private Signals Who Updates: JimLewis, Add YourName , ... Date Proposed: 2014 11 12 (extracted from SemaphoreDataStructure...
Attributes for PSL Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 17 Date Last Updated: 2012 08...
PSL Harmonization Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2014 03 30 Date Last Updated: 2014 03 30...
P1076 Working Group Public Documents These documents are for anyone with interest in the IEEE P1076 Working Group P1076 wg individual 2015.doc: P1076 Working...
Random Stimulus Generation Proposal Information Who Updates: JimLewis, ... Date Proposed: 2011 07 16 Date Last Updated: 2012 11 29 Priority:...
Operations on Ranges Proposal Editing Information Who Updates: Add YourName , ... Date Proposed: Date Last Updated: Priority: Complexity...
Raw Requirements, Originally on Bottom of Page Timing Information similar to SDC in VHDL See proposal: TimingConstraints include timing information in native...
File IO for ROM Proposal Information Current Owner: JimLewis, ... Contributors: JimLewis, PatrickLehmann, ... Date Proposed: 2014 June 19 Date...
Real Matrix Package Proposal Information Who Updates: DavidBishop, JimLewis, ... Date Proposed: 2013 11 13 Date Last Updated: 2013 11 13 Priority...
Recommend Error Messages Proposal Details Who Updates: ... Date Proposed: 2011 08 10 Date Last Updated: 2011 08 10 Priority: Complexity:...
Record Indexing OBSOLETE Merged into Record Introspection Indexing Proposal Details Who Updates: Brent Hayhoe Date Proposed: 2014 03 09 Date Last...
RecordIntrospection Use Case `ToJson` This use case demonstrates the usage of the proposed introspection capabilityto convert a complex data structure (nested records...
Record Reflection Use Case To Std Logic Vector So one of the things I frequently have to do is transform record types to and from std logic vector. Vendor provided...
Defining Interface Bundles Based on Record Types or Array Types An Analysis Ernst Christen, September 30, 2015 Updated October 8, 2015: Clarifications and corrections...
Regular Expressions Proposal Details Who Updates: DanielKho, Add YourName Date Proposed: 2015 01 03 Date Last Updated: Priority: Complexity...
Relaxed OTHERS Rules for Aggregates Proposal Information Who Updates: RyanHinton Date Proposed: 2013 10 10 Date Last Updated: 201 10 10 Priority...
Removal of Deltas Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus: Performance Requirement...
Remove Deprecated Constructs Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus: Performance...
Remove guarded blocks and signals Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority: Complexity: Focus...
Remove incremental port binding, groups, pulse rejection limit Recommendation: Reject Proposal Information Who Updates: Date Last Updated Priority...
Repair Example in Section 14.2 Proposal Details Language Version: VHDL 2008 Classification: LRM Correction Summary: One of the examples in LRM section...
Repair LRM Section 16.8.2.4.3 Missing Paragraph Text Proposal Details Who Updates: Brent Hayhoe Date Proposed: 2014 01 31 Date Last Updated: Priority...
Repair example in LRM section 5.6.3 Proposal Details Who Updates: TristanGingold Date Proposed: 2014 11 18 Date Last Updated: Priority: High...
Repair Example in Section 23.21 Proposal Proposal Details Language Version: VHDL 2008 Classification: LRM Correction Summary: One of the examples in...
Repair Wording of 6.5.72 Proposal Details Who Updates:TristanGingol, DavidKoontz Date Proposed:2014 11 20 Date Last Updated: Priority: Complexity...
Report Calling Path of Subprogram Proposal Details Who Updates: PatrickLehmann Date Proposed: Date Last Updated: 2016 Feb 19 Priority: Complexity...
Required Simulation Resolution Proposal Information Current Owner: JimLewis, ... Contributors: JimLewis, ... Date Proposed: 2013 Dec 23 Date Last...
Requirement Name Proposal Details Who Updates: Date Proposed: Date Last Updated: Priority: Complexity: Focus: Current Situation Requirement...
Overview of SystemVerilog Interfaces Introduction The concept of an interface has been part of SystemVerilog since the Accellera 3.0 version of the language. According...
Semaphores Analysis of Issues for Creating Semaphores in VHDL Who Updates: JimLewis, Add YourName , ... Date Proposed: Date Last Updated: Priority...
Sequential Signal Declarations Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 19 Date Last Updated...
Shorthand Subprogram Declarations Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 19 Date Last Updated...
Signal Pools Proposal Details Who Updates:Main.KevinCameron Date Proposed: Date Last Updated: Priority: Complexity: Focus: Current...
Simulation Controls Proposal Details Who Updates: Date Proposed: Date Last Updated: Priority: Complexity: Focus: Requirement Simulation...
Slicing Multidimensional Arrays Proposal Details Who Updates: Ryan Hinton, Date Proposed: Date Last Updated: Priority: Complexity: Focus...
Semi Complex RTL Record Based SPI Interface Use Case Introduction The SPI bus having existed since slightly before the wheel, it presents a familiar use case to introduce...
Revised SPI Example What is SPI? SPI refers to any number of variations on a 4 wire serial bus. The master asserts the chip select (usually active low) and then performs...
Standard package updates Proposal Information Who Updates: RyanHinton Date Proposed: 2013 04 18 Date Last Updated: 2013 04 18 Priority: Complexity...
The idea proposed here is to use a standard preprocessor like cpp or m4. For that to work, a standard set of pre defined variables is still needed that reflect the...
Std ulogic, Resolved, and ` ` Proposal Information Current Owner: JimLewis, ... Contributors: JimLewis, ... Date Proposed: 2014 June 19 Date Last...
In Bugzilla 104, it is indicated that an implicitly defined TO STRING has no specified representation for extended identifiers. The following change is proposed to...
Support Synthesis of Reals Proposal Details Who Updates: JimLewis, DanielKho, Add YourName Date Proposed: Date Last Updated: Priority:...
Redundant: Syntax Regularization between Entity and Component Proposal Information Who Updates: OPEN, JimLewis Date Proposed: 2014 03 23 Date Last...
Synthesizable `event Attribute Proposal Details Who Updates: DanielKho, JimLewis, Add YourName Date Proposed: 2015 01 02 Date Last Updated:...
Synthesizable Reports and Assertions Proposal Details Who Updates: DanielKho, ... Date Proposed: Date Last Updated: Priority: Complexity...
Textio bit vector read vs. std ulogic vector read Proposal Information Who Updates: JimLewis, , ... Date Proposed: 2013 11 14 Date Last Updated:...
Describe Timing Constraints Proposal Details Who Updates: DanielKho, Add YourName Date Proposed: 2015 01 01 Date Last Updated: Priority:...
Language Change Specification for Deferred Shared Variables Proposal LCS LCS Number: LCS 2016 080 Version: 1.0 Date: 24 Jul...
Truth Tables Proposal Editing Information Who Updates: Add YourName , ... Date Proposed: Date Last Updated: Priority: Complexity:...
Complex RTL Record Based CPU Interface Use Case Introduction The concept of this use case is to arbitrarily introduce a fairly complex block and interface structure...
AHB Lite Interface Example Code Support Package for AHB Lite Protocol library ieee; context ieee.ieee std context; package amba ahbl pkg...
AHB Lite Modified Interface Example Code Support Package for AHB Lite Protocol library ieee; context ieee.ieee std context; package amba...
IR2067: Logical link interface abstraction Description of Problem It is quite common that one logical connection between two component instances consists of several...
IR2089: Directional Records Description of Problem For many standard interfaces, for instance a bus, there are input and signals. Both can be combined into a record...
4. Current Capabilities At a bare minimum an interface is a composite with a method to group the subprograms together. To some degree, this can be done using a record...
7. Historical Discussion 7.1. Phone Discussion with Cliff Notes from Cliff on SV Interfaces Interfaces are good but often overhyped. Testbench ip developer can...
5. Things Reflected upon for VHDL 2008 revision, and then we ran out of time. These are not solutons for going forward 5.1. Composites: Resolving Values vs. Specifying...
6. Interface Implementation 6.1. Base line Implementation Interfaces are a methodology. As such to implement them, it is permissible to leverage existing constructs...
2. Introduction An interface is an abstract representation of the connectivity and communication between two or more objects. This abstract representation may be implemented...
Accellera VHDL TC Extensions SC Interfaces Jim Lewis, SynthWorks jim #64;synthworksNOSPAM.com Version 0.1 Draft, 12 Jan 2006 Abstract This paper covers the requirements...
3.2. RTL Design 3.2.1. Simple Bundles Connectivity of RTL functions consists of one or more signal objects. A bundle is a simplified form of an interface that allows...
3.2. RTL Design, Subprogram Usage, and Hardware Creation 3.2.3. Simple Interfaces A simple interface packages subprograms with bundles. A block (such as B1) calls...
3.1. Transaction Based Testbench 3.1.1. Basic Transactions A transaction is an operation on a device interface. As such it could be a cpu read or a cpu write. A transaction...
Minimal RTL Record Based Interface Use Case Assumptions This use case is intended to propose a minimal implementation of an enhanced interface support for RTL...
Candidate: Resolved Records Use records as an inout and require that each element of the record have a resolution function. This methodology is currently under usage...
Interface Construct and Port Mode Configurations Implementation details Interface Construct: interface declaration :: interface identifier of composite subtype...
Add a `Bus` port mode for bidirectional port signals Proposal: Add a new mode in addition to (in, out, buffer, inout, linkage), tentatively called `bus`.`bus` is...
Interfaces: Packages as an Interface Construct Current VHDL: The Basics Signals declared in a package are accessible to any model that accesses the package. For each...
VHDL 200X FT 17 Composite Interface Mode Enhancement Detail: Give VHDL the ability to specify the IO mode of an element of a record. Useful for testbenches and...
Unions and/or Variant Records Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 11 19 Date Last Updated:...
Unique Condition This was originally VHDL Issue Number 2012 Proposal Details Who Updates: Date Proposed: Date Last Updated: Priority: Complexity...
Update std logic arith Proposal Editing Information Who Updates: OPEN, JimLewis Date Proposed: 2012 08 17 Date Last Updated: 2012 08 17 Priority...
Allow the use of Unicode Proposal Details Who Updates: MartinThompson Date Proposed:8 Aug 2011 Date Last Updated: 8 Aug 2011 Priority: Low...
User Defined IO Rules Proposal Details Who Updates:Main.KevinCameron Date Proposed: Date Last Updated: Priority: Complexity: Focus:...
VHDL 201x Interface Implementation Proposal Updates 2016/04/21 replaced `element` keyword with record/array. added resolution to object feature...
This approach is to standardize on a set of pragmas(simple tool directive) that today are a proprietary pragma definition or structured comment in the VHDL language...
Standard VHDL Preprocessor The proposed solution is a standard set of preprocessing directives. It should properly fit with the VHDL standard tool directive that was...
Type Introspection on Vector Literals Proposal Information Who Updates: JimLewis, ... Date Proposed: 2011 07 15 Date Last Updated: 2011 07 15...
P1076 10 Aug 2011 Voting Vote closed at 5pm US PDT, on Wednesday 10 August, 2011. At the July 28, 2011 meeting it was decided to propose that the working group policies...
P1076 13 July 2011 Voting Item 1: Operating Procedures for P1076 Working Group http://www.eda.org/vasg/docs/p1076 wg pp.pdf Approve Negative Abstain...
P1076 Voting Information Call for Vote closes 10 Aug 5 pm Pacific To vote, you must, have a twiki account (Participating) and add yourself...
Name Type Size Values Tooltip message Attributes Member label Full TWiki username, e.g. main.FirstnameFamilyname. \...
WG Ballot Header The part between the horizontal rulers gets included by every contact topic. Ballot of Set VOTEUSEREDITMODE text Status: Related:...
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Level Sensitive Wait Proposal Information Current Owner: JimLewis, ... Contributors: JimLewis, ... Date Proposed: 2014 June 22 Date Last Updated...
Repeat count for wait Proposal Editing Information Who Updates: JimLewis, Add YourName , ... Date Proposed: 2012 08 19 Date Last Updated: 2012...
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