Heterogeneous Interfaces in VHDL

Proposal information

  • Who Updates: ErnstChristen, ...
  • Date Proposed: 2015-03-05
  • Date Last Updated: 2015-11-05
  • Priority:
  • Complexity:
  • Focus: General use, extensibilty

Proposal content

Several of the other proposals for supporting an interface concept in VHDL are based on an extension of the type system, which requires that all elements of the interface, i.e. the ports bundled by the interface, belong to the same object class. For VHDL 2008 this seems OK, but there are requirements to also allow shared variables as entity ports, and VHDL-AMS already supports quantity ports and terminal ports.This suggests that to support future needs an approach based on just extending the type system is not sufficient. The attached white paper collects requirements, reviews different proposals for an interface construct, and investigates possibilities for supporting a heterogeneous interface concept.

Based on use cases and agreed requirements, some of the ideas outlined in the white paper have been reworked. Two avenues are explored, one that reuses as much as possible of the existing VHDL concepts and therefore may appear wordy, and one that emphasizes compactness more at the cost of having to add more new concepts.

Heterogeneous Interfaces with Emphasis on Reusing Existing VHDL Capabilities

Heterogeneous Interfaces with Emphasis on Compactness

Questions

Comments

Arguments FOR

Arguments AGAINST

Supporters

-- ErnstChristen

-- ErnstChristen - 2015-05-28

Topic attachments
I Attachment Action Size Date Who Comment
PDFpdf VHDLHeterogeneousInterfaces.pdf manage 109.8 K 2015-05-28 - 01:06 ErnstChristen Heterogeneous Interfaces in VHDL
Topic revision: r4 - 2015-11-06 - 01:17:54 - ErnstChristen
 
Copyright © 2008-2019 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback