IR2089: Directional Records

Description of Problem

For many standard interfaces, for instance a bus, there are input and signals. Both can be combined into a record type individually, but not together. Event though both belong together (e.g. request+address from master to bus, ack+read_data in reverse direction) , they always have to be listed separately. The use of inout for ports is a bad alternative.

Proposed Resolution

I propose a keyword "reverse" or "backwards" or similar in record definitions. If such a record is used in a signal or variable declaration, it is irrelevant. However in a port declaration, the "reversed" record components have the reverse direction. In the example it would be:

    entity CPU is 
    port(
         bus_master : out Tmybusmaster 
            ...
    );
    
    where Tmybusmaster is declared as 
    
    TYPE Tmybismaster is RECORD
                request : std_logic;
                address : std_logic_vector(31 downto 0);
                ack : BACK std_logic;
                error : BACK std_logic_vector(5 downto 0);       
    END RECORD; 

ack and error would be inputs, though they are part of an OUT-record. The binding in an instantiation is not a problem I think, because we could as well bind the input and output parts individually. This is just "syntactic sugar".

Topic revision: r4 - 2016-11-15 - 18:23:41 - BrentHahoe
 
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