VHDL-200X FT-17 Composite Interface Mode

Enhancement Detail:

Give VHDL the ability to specify the IO mode of an element of a record. Useful for testbenches and system modeling.

type IfRecType is record
  Sig1 : std_logic ;
  Sig2 : std_logic ;
  Sig3 : std_logic_vector(7 downto 0) ;
  Sig4 : std_logic_vector(7 downto 0) ;
end record ;

Mode IfRecType_Mode_Model1 : IfRecType := (
  Sig1 => in,
  Sig2 => out,
  Sig3 => inout, 
  Sig4 => in 
) ; 
Mode IfRecType_Mode_Model2 : IfRecType := (
  Sig1 => out,
  Sig2 => in,
  Sig3 => inout, 
  Sig4 => in 
) ; 

Entity Model1 is
port (
  IfRec1 : IfRecType_Model_Model1 : IfRecType ;
  . . .
Topic revision: r3 - 2016-11-15 - 18:23:42 - BrentHahoe
 
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