P1076 Proposals and Requirements

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Sections:


Proposals Section

Details of and links to all proposal.

Proposal Summary + Link to Proposals

Status Values

  • RAW - initial development, may change frequently, comments welcome
  • RFC - draft, needs comments
  • REVIEW - requesting more formal review in working group meeting
  • STABLE - done

Item Who Status Rank Description Supporters Priority
Interface Related Proposals          
Interface and Bundle Enhancements P1076Group In Progress 22 WG generated interface and bundle enhancements  
Partially Connected Vectors on port map KevinJennings RFC 1 Allows a port map vector (array) range slice to be left open.  
NewBusModeForBidirectionalPortSignals BrianDrummond   40 Add a "Bus" port mode for bidirectional port signals  
Protected Types with Public Signals JimLewis   44    
Interface Construct and Port Mode Configurations BrentHayhoe   45    
Packages as an Interface Construct JimLewis   53    
Implicit Parameter and Port Connections JimLewis - 54 Shorthand notation for parameter and port maps  
Bidirectional Connections KevinCameron   70 Enable modeling of bidirectional components  
Closely related record types RyanHinton RFC 75    
           
Converting Things, Generally          
Extend IMAGE attribute to arrays and records Ryan Hinton RFC 12 Extend IMAGE attribute and/or TO_STRING implicit function to composite types: arrays and records.  
Record Introspection ChrisHiggs - 41 Convert between a record and a vector  
Record Introspection & Indexing Brent Hayhoe RFC 69 Proposal to allow indexing and scanning of elements within record structures. MERGED (WAS: Member attribute for records)  
           
Language Regularization Proposals          
Allow access types and protected types on Function Interface JimLewis - 2 -  
Protected Type Methods with Parameters that are Access Type, Protected Type, or File Type JimLewis   4 Method Parameters with access types  
Sequential Declaration Regions JimLewis - 7 -  
Composites of Protected Types JimLewis   14 Arrays and records containing protected types  
Protected types and aliases JimLewis   17    
Sizing from initial values RyanHinton - 19 Allow signal and variable constraints to be deduced from initial values. This is already allowed for constants, but this proposal extends the capability to variables and signals.  
Relax Library Requirement on Configurations CliffordWalinsky RFC 23 Allow configurations to reside in different libraries from their corresponding entities.  
Conditional Expressions and/or Operator CliffordWalinsky,   36 Allow the use of conditionals in expressions and initializers.  
Stop Binary/Octal/Hex Read At Trailing Underscore CliffordWalinsky RFC 38 Revise the specifications for the textio binary, octal, and hexadecimal read procedures to terminate reading when a trailing underscore is encountered.  
Syntax regularization - End JimLewis   55 Particularly "End"  
Process-All and Implicit Signals Brent Hayhoe RFC 56 Allow implicit signals alongside the ALL keyword in sensitivity lists.  
Syntax regularization - Optional Semicolon BertDeJong RFC 71 Extra optional semicolon at end of interface_list  
Package Name Case Sensitivity JimLewis   79    
Syntax regularization - Empty records RyanHinton RFC 82 Allow record declations to have no members, analogous to a null array  
Conditional Return Statement JimLewis - 94 -  
           
2008 Boolean Write JimLewis Rejected 20    
           
Integer Proposals          
Integers of arbitrary length MartinThompson RFC 8 Add integers of arbitrary length  
Long Integers 64 bit type CliffordWalinsky - 26 Add a type for 64 bit integers, separate from integer  
Modular Integer Types MartinThompson - 31    
Additional Operators for Integers - logic JimLewis   51 Add Logic Operators for Integers  
Implicit Conversions for Like Types JimLewis   81 Addresses issues with assigning integer literals to unsigned, signed, real literals to ufixed, sfixed, and float, and vice-versa. Obviously with some constraints.  
Extended Integers DanielKho RAW   Require a minimum of 64 bits for integers.  
Physical Type Range KevinThibedeau     Require that user-defined physical types can cover the same range as time.  
Enhanced Integers JonasBaggett RFC None New derived integer types fittable for synthesis.  
           
Language Enhancement          
date and time system functions JimLewis - 11 -  
Modify Report Statement to return calling path of subprograms PeterFlake MartinThompson   15    
PATH_NAME and Shared Variables and Subprograms JimLewis - 32    
Anonymous Types on Interfaces JimLewis - 16 -  
Attributes for Enumerated Types JimLewis - 18 -  
DPI Proposal PeterFlake - 21 Direct interface to other languages  
Hierarchical Libraries ChrisHiggs - 25 library protocol.packet.ethernet  
External names for types JimLewis - 28 See Alternative Proposal. Needed to access the type of a statemachine from tesbench.  
Updates to standard packages - split into LRM and Packages RyanHinton RFC 29 Additions to LRM, standard, std_logic_1164, numeric_std, math_real, math_complex, and fixed_pkg  
Garbage Collection CliffordWalinsky   30 Garbage collection  
Composition with Protected Types JimLewis RFC 33 Composition with protected types  
Protected Types with Generic Clause JimLewis RFC 34 -  
Configuration Spec for Direct Instances RyanHinton RFC 37 Add a facility to write a configuration specification to control architecture selection possibly several hierarchy layers deep for a direct instantiation.    
Attributes for PSL JimLewis - 43 -  
Protected Types with Wait and Private Signals JimLewis   46    
Protected Type on Entity Interface JimLewis   47    
Map subprogram generics on call JimLewis RFC 49 -  
API for Assert JimLewis - 50 -  
Slicing Multidimensional Arrays RyanHinton   52    
External Non-Shared Variable Name Brent Hayhoe RFC   Add the ability to reference local process variables and pre-VHDL92 shared variables via the 'external name' syntax.  
Array type generics RyanHinton - 59 Indicate that a generic type is an array of another generic type.  
New Predefined Attributes: actual, and formal Brent Hayhoe RFC 60 Allow explicit selection of actual or formal part of an instantiated subprogram's parameter.  
Conditional Compilation Many - 61 solve tool-specific language issues  
Abstract Packages JimLewis - 62 -  
Wait with Level Check JimLewis   63 Wait with level sensitive check  
Unions and/or Variant Records JimLewis RAW 65 Need unions to describe coverage that can either be a range or a single value  
Expressions in Bit String Literals Brent Hayhoe RFC 66 Adds the facility to define the bit width of the string literal with an integer expression.  
Required Simulator Resolution JimLewis   67 Need construct or subprogram to specify minimum simulator resolution required by a design unit. It is an error for a simulation to enumerate with larger value.  
Relaxed OTHERS rules in aggregates RyanHinton RFC 68 Relax the rules for using OTHERS in array aggregates  
Function Knows Return Vector Size KevinJennings RFC 72 Allows functions to access attributes of the target of the function  
Deferred Shared Variables Brent Hayhoe LCS 80 Shared variables & protected types in same package.  
Remove Ordering Restrictions on Interface Lists CliffordWalinsky RFC 86 Allow entity and subprogram interface objects to refer to earlier objects of the same interface list.  
Operations on Ranges Need Owner   99 Support Operations on Ranges  
Overload Assignment Operator OPEN   102 Ability to overload the assignment operator := would be useful  
Extended String Literals JimLewis, DanielKho     Support C Style String Literals  
Extended Ranges PatrickLehmann RAW None Make ranges more powerful.  
Extended user-defined attributes PatrickLehmann RAW None Let users define new attributes, which for example map to functions.  
           
New proposals          
Link your new proposal here          

Someday Maybe Proposals

Item Who Status Rank Description Supporters Priority
Vector literal introspection JimLewis RFC 35 Distinguish between std_logic_vector and integer_vector literals  
Object Orientation     39 Links to different proposals  
Wait with a repeat count JimLewis - 48 -  
CrossLanguageInstances     73 Related to DPI  
Std_ulogic, Resolved, and '-' JimLewis   74 Resolution of '-' and 'Z' is 'X", ok for RTL, but bad for testbenches?  
Create natural_vector JimLewis   78 Create natural_vector as a subtype of integer_vector  
Architecture Generic LarsJensen RFC 83 Implements architecture instantiation through generics  
Multiple Top-Level Designs CliffordWalinsky Needs Work & Advocate 88 Allow designs to have multiple top-level roots. To be a common enhancement, it needs someone with a use case to work on it.  
Preponed Processes (clocks) JimLewis - 89 Desc  
Update std_logic_arith JimLewis   90 Update std_logic_arith to simplify interoperability with numeric_std  
Dynamic Process, Instances, Fork Join     91    
Shorthand Subprogram Declarations JimLewis - 92 -  
Sequential Signal Declarations JimLewis - 93 -  
Truth Tables Need Owner   98 Truth table for multi-input/multi-output  
Asynchronous Channels KevinCameron   100 Asynchronous channels (aka pipes)  
Clocked Shorthand DanielKho RFC 103 Shorthand to infer flip-flops and pipelining  
Dynamic Rewiring KevinCameron   105 Allow runtime re-elaboration and re-wiring  
Composing Paths to External Names JimLewis        
Attribute Shorthand DanielKho RAW   Shorthand to create attributes.  
Support Synthesis of Reals DanielKho RAW   Simplify synthesis of floating-point operations, by using real to encapsulate synthesizable fixed- or floating-point types.  
           

Rejected Proposals

Item Who Status Rank Description Supporters Priority
Predefined Attributes Can't Be Redefined CliffordWalinsky RFC 42 Prohibit predefined attributes from being redefined.  
Named Package Bodies JimLewis - 64 -  
Unique Condition - OrIf PeterFlake   76    
Synthesizable Reports and Assertions DanielKho RFC 77 Standardize constructs that allow reports and assertions to be able to be synthesized.  
Simulation Controls     84    
Additional Rules for Bit String Literals DanielKho RFC 85 Specify additional rules for string literals.  
Recommend Error Messages ChrisHiggs - 95 Standard format for error messages  
Mixed Signal Support KevinCameron   96 Support multiple types driving/receiving on a wire [
Multicycle Path Specification     97 Speciification of multi-cycle paths in language syntax  
AtomicComposites Needs Owner   101    
Operators Overloading for Protected Types Need Owner   104 Operator Overloading for Protected Types  
2 and 4 State values Needs Owner   108    
Specifying Timing Constraints DanielKho RAW   Allows RTL designers to specify timing constraints directly from HDL.  
Synthesizable 'event Attribute DanielKho RAW   Synthesize 'event for DDR FFs.  
Object Inspection JingPang RAW   Method to do introspection on names, find different objects and find all instance labels whose component is xyz.  
           

Change Proposals for IEEE Packages

Item Who Status Rank Description Supporters Priority
numeric_std, fixed and float bugs and consistency updates DavidBishop   3 Bug fixes and consistency updates for numeric_std, fixed_generic_pkg.vhd, and float_generic_pkg.vhd  
Real Matrix Math Package DavidBishop REVIEW 5, 10, 13 Matrix Math User's Guide (pdf)
Packages (zip)
Must Do
Fixed point Algorithmic User's Guide (pdf) DavidBishop REVIEW   Package (zip)  
Floating point Algorithmic User's Guide (pdf) DavidBishop REVIEW   Package (zip)  
File IO / TextIO updates JimLewis - 6 -  
Flag metavalues detected by ?? JimLewis   9    
Read differences of bit_vector and std_logic_vector JimLewis   27    
Updates to standard packages - split into LRM and Packages RyanHinton RFC 29 Additions to LRM, standard, std_logic_1164, numeric_std, math_real, math_complex, and fixed_pkg  

ISAC and Items that Must Do

Item Who Status Last Modified Description Supporters Priority
P1735 Encryption Updates JarekKaczynski JohnShields STABLE   Adopt Recommendation from P1735 Must Do
P1735 Visibility Updates StevenDovich     Alignment with P1735 visibility model Must Do
Signatures for Association List Aspects CliffordWalinsky RFC   Describes how to resolve ambiguous mappings of subprograms to overloaded interface subprograms in generic map aspects. Must Do
Assigning 2008 Entities to Attribute Classes CliffordWalinsky RFC   Describes how subprogram instances, interface subprograms, package instances and interface packages match entity classes in attribute specifications. Must Do
Repair LRM Example 14.2 CliffordWalinsky     Fix for one of the examples in LRM Section 14.2. Must Do
Repair LRM Example 7.3.2.1 DanielKho RFC   Fix the example in 7.3.2.1. Must Do
Repair Text on Context Clauses DanielKho RFC   Fix the LRM's text for context clauses. Must Do
Repair LRM Section 16.8.2.4.3 Missing Paragraph Text Brent Hayhoe RFC   Correct section header numbering in VHDL 2008 LRM. Must Do
Repair example in LRM section 5.6.3 TristanGingold     Fix example in 5.6.3 Must Do
Bit String Literals Corner Cases TristanGingold     Fix minor issues in 15.8 Must Do
Repair Generate Statements TristanGingold     Fix wording and feature Must Do
Force an Out Port Many       ISAC Must Do
Precedence of Unary Logical Operators JimLewis       ISAC Must Do
String representation for extended identifiers PeterFlake       ISAC Must Do
Alternate Label in Path Name bug 293 PeterFlake       ISAC Must Do
Repair Example in Section 23.21 Proposal RadoslawNawrot     Fix for LRM VHPI example Must Do
Typographical Issues in IEEE Std 1076-2008 Many     A collection of typographical issues in the LRM that don't have a separate page Must do
Process-All Should Not Be Sensitive to Signals in Packages CliffordWalinsky RFC   Ranking: 87 - Designs are in error if they have a process(all) block that calls a package's subprogram that references a signal. Since this error is costly to accurately verify, remove this requirement.  
Fix generic map rules TristanGingold       Must Do
           

Open Issues Looking for an Owner

Item Who Status Description Supporters Priority
VHPI Impact     VHDL-2008 impact to VHPI  
VHPI for PSL     PSL impact to VHPI  
PSL Harmonization OPEN     Update for 1850-2010  
define parameters for env.stop OPEN     Define standard parameters for env.stop  
Standard Instances of Float OPEN     Define standard instances of float_generic_pkg and fixed_generic_pkg  
Move definition of TEXT, INPUT, OUTPUT OPEN     Move definition of TEXT, INPUT, and OUTPUT  

VHDL AMS 1076.1 Proposals that go in 1076

The packages listed in this table are planned to be included in P1076.1-201x. In discussions a while ago with the P1076 WG some members expressed interest in these packages as well. Coordination between the WGs is required to ensure that the same versions are included in both places.

Item Who Status Last Modified Description Supporters Priority
Table Driven Modeling Joachim Haase et.al. Draft of reference implementation available 5/24/2012 The package supports the description of functional dependencies y = f(x1, x2, ..., xn) based on a number of (n+1)-tupels (y, x1, x2, ..., xn). Emphasis is on floating point functions, and various interpolation schemes are supported. More details, and a reference implementation can be found in a protected area of the P1076.1 web. High for P1076,1-201x.
Vector/matrix package David Bishop, Zhichao Deng     It's the same package listed in the next table High for P1076,1-201x.

Proposals for 1076.6 - Requires a Chair for this activity

This work would potentially be done by a separate working group. Requires a chair. JimLewis will help you through the IEEE process, but you will need to get vendor participation for the effort to be relevant.

Item Who Status Last Modified Description Supporters Priority
FSM Safe Design Brent Hayhoe RFC   Proposal to allow safe state identification for synthesis in FSM designs.  
Synthesis Attributes       Attributes for RAM, ROM, ... Define these in 1076?  
Assertions as Directives main.JimLewis     Support ZeroOneHot, ...  
SupportReal          
Synthesizable 'event          
           
           

Items to forward to open source package group

Item Who Status Last Modified Description Supporters Priority
File IO for RTL ROM JimLewis     Ranking: 24 - File IO for RTL ROM  
Functional Coverage JimLewis RFC   Implemented by open source group OSVVM  
Random Stimulus JimLewis RFC   Implemented by open source group OSVVM  
Semaphores          
Extended Hardware Functions - RTL Macros       RTL Macros. Meeting: Dec 15, 2011 and Mar 31, 2011  
Associative Arrays       See TBV Propoal 2  
Queues / FIFO       See TBV Proposal 4  
Sync and Handshaking       See TBV Proposal 7  
Memory / Sparse array       See TBV Proposal 12  
Loading and Dumping Memories       See TBV Proposal 18  
Lists       See TBV Proposal 19  
Create open source boost/C++ like libraries       Meeting: Dec 15, 2011  
to_integer and to_integer_vector JimLewis -   -  
Graphics Library DanielKho RAW   Implement a graphics library for VHDL.  
Regular Expressions DanielKho RAW   Implement VHDL regular expressions.  
           

Rejected Item Summary

Item Who Status Description Supporters Priority
Use of Unicode MartinThompson Reject Add unicode for strings, files, identifiers, comments  
Scope of Keywords JimLewis Reject Give names same scope as keywords  
Component Declaration derived from Entity Declaration JimLewis Reject Syntax that creates a component declaration from an entity decalaration and puts it into a specified package  
         
         

Items Subsumed by other items

Item Who Status Description Supporters Priority
           
Record Indexing Brent Hayhoe Subsumed   See:- Record Introspection & Indexing  
Signal Pools KevinCameron     Ranking: 106 - Alternative to wire-like communication for RF  
User Defined IO Rules KevinCameron     Ranking: 107 - Move rules about in/out/inout to types  
         
Withdrawn: Functions Know Output Subtypes OPEN RFC   Allows function to access subtype properties of the target.  
Redundant: Syntax regularazation Entity Component OPEN     Syntax regularazation between entity and component  
Protected Type Updates JimLewis -   Numerous  

Raw Requirements Lists

List Description Notes
ISAC Active IR List    
Old Meeting Action Item List Current Action Items now tracked in meeting minutes  
Bugzilla List    
IEEE VHDL 2008 Subgroup Lists (TBV, FT, DTA, )    
Accellera VHDL 2008 Remaining Items List    
Raw Requirements in Text of Original Page    

LCS Section

Details of all LCS documents.

LCS Documents for Balloting

LCS Proposal Ballot
LCS-2016-080 Deferred Shared Variables  
     

Approved LCS Documents

LCS Proposal Votes For Votes Against
       

Rejected LCS Documents

LCS Proposal Votes For Votes Against
       
Topic attachments
I Attachment Action Size Date Who Comment
Microsoft Excel Spreadsheetxls Accellera_RequirementsStatus_19May2006.xls manage 131.0 K 2011-09-08 - 15:09 JimLewis Accellera Requirements List from VHDL-2008
PDFpdf Corrections_to_the_Encryption_Flow_description_in_IEEE_Std_1076.pdf manage 204.8 K 2012-03-15 - 15:10 JarekKaczynski Based on the works of P1735 group
Texttxt Proposal.txt manage 2.8 K 2013-08-28 - 17:27 DavidBishop Instructions to fix bugs in "fixed_generic_pkg-body.vhdl", "float_generic_pkg-body.vhdl" and the fixed point documentaiton
Microsoft Excel Spreadsheetxlsx vhdl_requirements_priority.xlsx manage 16.1 K 2014-11-13 - 21:17 JimLewis VHDL Requirements Prioritization Sheet
Topic revision: r225 - 2016-11-28 - 11:25:47 - BrentHahoe
 
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