Describe Timing Constraints
Proposal Details
- Who Updates: DanielKho, <Add YourName>
- Date Proposed: 2015-01-01
- Date Last Updated:
- Priority:
- Complexity:
- Focus:
Current Situation
There is currently no standardized way to specify timing constraints from behavioral models. The Synopsys Design Constraints (SDC) format is a de-facto industry standard, but these constraints are applied as separate (non-HDL) files, which will later get applied during synthesis or placement-and-routing of the design.
Requirement
[In progress...]
Specify a standard way to describe timing constraints similar to SDC, but directly from the behavioral model (VHDL). Some of these constraints include:
- Specifying false paths.
- Specifying multicycle paths.
- Specifying clocks (period, duty cycle).
- Setting delays on input and output ports.
- Specifying input drive strengths (capacitance, slew rate/transition time).
- Specifying output loading (capacitance, slew rate/transition time).
- Specifying interconnect parasitics (pin / net capacitance or loading).
- Specifying maximum and minimum constraints (path delays, drive strengths, capacitive loadings, parasitics).
- Describing clock uncertainty (jitter).
Propose to standardize several predefined VHDL attributes for this purpose.
Implementation details
[In progress...]
The idea is to use a consistent method of decorating a signal, and consistent ways of making signal assignments for the signal.
Code Examples
[In progress...]
signal clk:std_ulogic:='0';
attribute period:time; attribute period of clk:signal is 10 ns;
attribute maxTransition:time; attribute maxTransition of clk:signal is 1.5 ns;
...
clk <= not clk after clk'period/2;
This is equivalent to setting the SDC constraints:
create_clock -name clk -period 10 [get_nets clk]
set_clock_transition -max 1.5 [get_clocks clk]
Use Cases
Arguments FOR
Arguments AGAINST
General Comments
Supporters
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--
DanielKho - 2015-01-01
Topic revision: r3 - 2020-02-17 - 15:35:00 -
JimLewis