TimingConstraints < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>TimingConstraints (2020-02-17, JimLewis) (raw view)EditAttach
---+ Describe Timing Constraints

%TOC%

---++ Proposal Details
   * Who Updates: Main.DanielKho, &lt;Add Main.YourName&gt;
   * Date Proposed: 2015-01-01
   * Date Last Updated:
   * Priority:
   * Complexity:
   * Focus:

---+++ Current Situation

There is currently no standardized way to specify timing constraints from behavioral models. The Synopsys Design Constraints (SDC) format is a de-facto industry standard, but these constraints are applied as separate (non-HDL) files, which will later get applied during synthesis or placement-and-routing of the design.

---+++ Requirement

[In progress...]

Specify a standard way to describe timing constraints similar to SDC, but directly from the behavioral model (VHDL). Some of these constraints include:
   1 Specifying false paths.
   1 Specifying multicycle paths.
   1 Specifying clocks (period, duty cycle).
   1 Setting delays on input and output ports.
   1 Specifying input drive strengths (capacitance, slew rate/transition time).
   1 Specifying output loading (capacitance, slew rate/transition time).
   1 Specifying interconnect parasitics (pin / net capacitance or loading).
   1 Specifying maximum and minimum constraints (path delays, drive strengths, capacitive loadings, parasitics).
   1 Describing clock uncertainty (jitter).

Propose to standardize several predefined VHDL attributes for this purpose.

---+++ Implementation details

[In progress...]

The idea is to use a consistent method of decorating a signal, and consistent ways of making signal assignments for the signal.

---+++ Code Examples

[In progress...]
<pre><verbatim>signal clk:std_ulogic:='0';
attribute period:time; attribute period of clk:signal is 10 ns;
attribute maxTransition:time; attribute maxTransition of clk:signal is 1.5 ns;
...
clk <= not clk after clk'period/2;</verbatim>
</pre>

This is equivalent to setting the SDC constraints:
<pre><verbatim>create_clock -name clk -period 10 [get_nets clk]
set_clock_transition -max 1.5 [get_clocks clk]</verbatim>
</pre>

---++ Use Cases
---++ Arguments FOR

---++ Arguments AGAINST

---++ General Comments

---++ Supporters

_Add your signature here to indicate your support for the proposal_

-- Main.DanielKho - 2015-01-01
Topic revision: r3 - 2020-02-17 - 15:35:00 - JimLewis
P1076/Ballots