VHDL-2008-TBV Review

Item Description Tracking / Proposal Reviewed On Supporters Priority
  TBV Proposals P1076.Vhdl2019ActionItems    
TBV 6 Assign image values for identifier-based enumeration type values Drop June 27, 2013  
TBV 9 Expected Value Detectors Drop. Not enough information. June 27, 2013  
TBV 13 Object Orientation Add to proposal list and address during ranking June 27, 2013  
         
TBV 1 Vectors (boolean, Integer, real) Done/2008 May 24, 2012  
TBV 2 Associative Arrays Package    
TBV 3 Fork and Join Assigned May24, 2012  
TBV 4 Queues / FIFO Package May24, 2012  
TBV 5 Improved Textio Done/2008    
TBV 7 Sync and Handshaking Package May24, 2012  
TBV 8 Request Action / Wait for Action TBV7 May24, 2012  
TBV 10 Access to coverage for reactive TB Functional Coverage    
TBV 11 Hierarchical Signal Reference Done/2008    
TBV 12 Sparse Arrays - Memories - small or large Package    
TBV 14 Random Value Generation with optional and dynamic Weighting Random Stimulus    
TBV 15 Random Object Initialization Random Stimulus    
TBV 16 Random 2 state value resolution in place of X generation Random Stimulus    
TBV 17 Random choice selection with optional and dynamic weighting Random Stimulus    
TBV 18 Loading & dumping memories Package    
TBV 19 Lists Package    

VHDL-2008-DTA Remaining Items

Item Description Tracking / Priority Reviewed On Supporters Priority
  Data Types and Abstractions Proposals      
OO -      
Dynamic Processes -      
Reconfigurable Computing -      
Suave Proposal Suave Peter Ashencen, Philip Wisley, Dale Martin      

VHDL-2008-FT Remaining Items

Item Description Tracking / Proposal Reviewed On Supporters Priority
  VHDL-200X Fast Track Proposals      
FT10A

Conditional expressions with IF/when. Need proposal that hanldes initializers with possible extensions.

*Need Proposal*

July 18, 2013  
FT15 Slicing of multidimensional arrays and arrays of arrays Ryan to add updated proposal May 9, 2013  
FT17 Interfaces Interfaces May 9, 2013  
FT27 Make architecture optional / allow RTL code in entity Reject May 9, 2013  
FT32 Peter Ashenden Analysis Discussion Rollup

Done.

Implemented with External Names in 2008 see section 8.7

May 9, 2013  
VHPI Impact   Copied to Open VHPI list May 9, 2013  
VHPI for PSL   Copied to Open VHPI list May 9, 2013  

VHDL-2008-MP Remaining Items

Item Description Tracking / Proposal Reviewed On Supporters Priority
  MP Proposals      
MP 1 Bidirectional Connections (Jumper - static, Switch - dynamic, Resistor) Bidirectional Connections May 9, 2013  
MP 2 Regularized and minimized bracketing (end) Accept if someone champions it. May 9, 2013  
MP 6 Allow attribute declarations in code regions (not just declaration regions) Not for this revision. No compelling arguments. June 13, 2013  
MP 8 Make transport the default delay model Not for this revision. Issues with backward compatibility. June 13, 2013  
MP E1 Allow ";" to terminate as well as separate interface lists Ryan to write proposal May 9, 2013  
MP E2 Eliminate passive statement restriction on entities Drop. Benefits? Aug 1, 2013  
MP Allow subprogram bodies in package declarations Not for this revision. Benefits? June 13, 2013  
MP Ability to apply register kind semantics to std_logic. Retain last resolved value when all drivers are off Drop. Not clear. June 13, 2013  
MP Remove white space requirement in physical literals Drop. Potential ambiguity with literals with 'e' in them and bit string literals.

June 13, 2013

June 27, 2013

 
MP Short alias name for std_logic_vector Drop. Concerns about conflicts. June 13, 2013  
MP Value folding of std_ulogic (2 state/4 state) Drop. Not clear. June 13, 2013  
MP Implicit generic/port map in component instance Implicit Parameter and Port Connections Have Proposal  
MP Add Endif (like elsif) Drop. If we add EndIF then we need EndProcess, EndArchitecture.... June 13, 2013  
MP One_hot assertion to remove priority from if-then-elsif Need Proposal. June 13, 2013  
MP Longest static prefix issue with loops Drop.

June 13, 2013

June 27, 2013

 

VHDL-2008-Performance Remaining Items

Item Description / Proposal Recommend Reviewed On Name + Priority
  Performance Proposals      
Perf 1 Removal of simulation deltas Reject Jan 31, 2013 BAH -10
Perf 2 Expressions in sensitivity list - ie: posedge Reject Jan 31, 2013 JimLewis -10 BAH -10
Perf 3 Define 2 & 4 state semantics for std_ulogic Investigate Further Jan 31, 2013 BAH ±0
Perf 4 Light-weight signals Reject Jan 31, 2013 BAH -10
Perf 5 Atomic composite signals Investigate Further Jan 31, 2013 BAH +5
Perf 6 Remove deprecated constructs Reject Feb 21, 2013 BAH -5
Perf 7 Clocks & Zero-delay ordering of signals Reject Feb 21, 2013 BAH -10
Topic revision: r2 - 2020-02-17 - 15:47:53 - JimLewis
 
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