Interface Discussions

Pages for the bullet points and questions relating to various aspects of the proposed new Interface construct.

Heterogeneous Interface Requirements

A basic set of requirements as originally set down in the whitepaper attached to Ernst's Proposal HERE.

Interface Mode Requirements

Requirements relating to port/parameter mode extensions required for a simple CPU master/slave(s) interface example.

Interface Bundle Requirements

Requirements relating to bundling of types and objects for interfaces.

Overview of SystemVerilog Interfaces

Includes thoughts how the functionality relates to VHDL concepts.

Additional required proposals

Additional existing proposals to be incorporated with the new Interface Construct.

Bundles in VHDL

Discussion of issues around defining a concept of a bundle (or interface) in VHDL

• Brent Hayhoe Comment: Simple Record Form of Bundle Usage
• Daniel Kho Comment: Options for using generics with Bundles

Status Quo and Moving Forward

Summing up of where we are and how to proceed further.

Accepted requirements from WG meetings

Collection of definitive requirements for an interface construct and specifying a bundle.