interface CPU_if is
generic(
DATA_WIDTH : Integer;
ADDR_WIDTH : Integer;
TOTAL_SLAVES : Integer
);
subtype DATA_st is Std_Logic_Vector(DATA_WIDTH - 1 downto 0);
subtype ADDR_st is Std_Logic_Vector(ADDR_WIDTH - 1 downto 0);
type SLAVE_SEL_at is array TOTAL_SLAVES - 1 downto 0 of Std_Logic;
type SLAVE_DATA_at is array TOTAL_SLAVES - 1 downto 0 of DATA_st ;
modport MASTER_mp is
signal DATA : buffer DATA_st;
signal ADDR : buffer ADDR_st;
signal R_W : buffer Std_Logic;
signal SLAVE_SEL : buffer SLAVE_SEL_at;
signal SLAVE_DATA : in SLAVE_DATA_at;
end modport MASTER_mp;
modport SLAVE_mp is
MASTER_mp'converse;
end modport SLAVE_mp;
end interface CPU_if:
modport SLAVE_mp is
generic(
SLAVE_SEL_g : Integer
);
signal DATA : in DATA_st;
signal ADDR : in ADDR_st;
signal R_W : in Std_Logic;
signal SLAVE_SEL : composite SLAVE_SEL_at(
SLAVE_SEL_g : in;
others : null
);
signal SLAVE_DATA : composite SLAVE_DATA_at(
SLAVE_SEL_g : buffer;
others : null
);
end modport SLAVE_mp;
type CPU_r is
record
DATA_l : DATA_st;
ADDR_l : ADDR_st;
R_W_l : Std_Logic;
SLAVE_SEL_al : SLAVE_SEL_at;
SLAVE_DATA_al : SLAVE_DATA_at;
end record CPU_r;
modport MASTER_mp is
signal CPU : composite CPU_r(
DATA_l : buffer;
ADDR_l : buffer;
R_W_l : buffer;
SLAVE_SEL_al : buffer;
SLAVE_DATA_al : in
);
end modport MASTER_mp;
modport SLAVE_mp is
generic(
SLAVE_SEL_g : Integer
);
signal CPU : composite CPU_r(
DATA_l : in;
ADDR_l : in;
R_W_l : in;
SLAVE_SEL_al : composite SLAVE_SEL_at(
SLAVE_SEL_g : in;
others : null
);
SLAVE_DATA_al : composite SLAVE_DATA_at(
SLAVE_SEL_g : buffer;
others : null
)
);
end modport SLAVE_mp;