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P1076 August 21, 2014 Meeting Minutes
Attendees:
JimLewis
*
CliffordWalinsky
*
PeterFlake
*
RyanHinton
*
MartinThompson
Agenda:
Action Item Review
Ranking Criteria
Review and Approve Meeting Minutes:
Next Meeting: Thursday August 28, 2014 8 am Pacific
Previous Meeting: Thursday August7, 2014
Action Item Review
Done before meeting
Ryan:
to_string and 'image for composites
Discussion
Integers: Arbitrary vs. Fixed Size?
WRT efficiency 64 bit is good and arbitrary can be more work on implementation
Python and Ruby both use unbounded integers
Ryan, Martin, Jim are leaning toward arbitrary width
Cliff - compiler integer vs arbitrary width integer is going to be challenging
Performance can be poor
For a design with integer, recompile it with arbitrary integers and it may run much slower.
Thinks we need a separate type and package.
Create new arbitrary integer type and make it closely related to integer
Seems reasonable since integer and real are closely related
Could port a bignum library to VHDL using integer_vector
Integers and Logic Operations
Should bitwise operations be supported for integers without requiring modulo operations?
Allowing them may put constraints on synthesis optimizations
Martin - 2033 - Increment operator with modulo wrap around.
Proposal at
ModularTypes
Have two separate suggested implementations
Deferred
Need more reviewers of matrix math package
Ryan: Arbitrary width real: see
Nov 8 2012 meeting
Open - Multi dimensional Array restructuring: Array <--> Matrix Transformations
2012_MeetingJuly19
MeetingDecember15
Matlab has built-in reshape functions
In VHDL - explicit vs implicit defined operator
David Bishop: Requiring an implicit operator could delay implementations
Can this be handled by anonymous types on interfaces or generics on a package?
Language facility for creating implicit operators?
Ryan - Slicing Multidimensional Arrays (FT15) maybe related to above
2012_MeetingMay24
Jim - Mark bugzillas for which we have a proposal with that status
Jim - Table driven modeling via protected types
2012_MeetingMay10
Open - technical leader for 1076.6 activities?
std_logic_1164 uses 1076.6 attribute "RTL_SYNTHESIS_OFF" and "RTL_SYNTHESIS_ON"
Ranking Criteria
Rank based on need
Item needs to be fixed
Useful for an application
Rank based on complexity
How hard to implement
Noted several items in Collected Requirements as Must Do
AI: Jim: Create ranking sheet.
Review and Approve Meeting Minutes:
Motion: Ryan 2nd: Peter
Next Meeting: Thursday
August 28, 2014
8 am Pacific
Previous Meeting: Thursday
August7, 2014
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Topic revision: r3 - 2020-02-17 - 15:36:13 -
JimLewis
P1076
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