P1076 July 19, 2012 Meeting Minutes

Attendees:

• JimLewis * MartinThompson * JarekKaczynski * PeterFlake * RyanHinton * DanielKho

Agenda:

• Login to get the Dial-in Information
• Approve June 21 Meeting Minutes. Motion: JarekKaczynski 2nd: PeterFlake
• Call for proposals for new items
• Call for volunteers to work on proposals
• Looking for team leader for ISAC
• Review updated proposals
  • RSS of recent changes
• Review requirements lists from VHDL-200X/Accellera effort
  • Assign owners to raw items and work toward proposals
• Review items in the collected requirements list
• Review ISAC issues and Bugzilla

Record IO

• Simple Bundles - maybe enough for RTL design
  • Wishbone and variants use a model of a single master and single slave and handle arbitration between multiple masters and multiple slaves in an interconnect block - which simple bundles would handle just fine.
• Variant Bundles - nice but benefit may not justify cost of complexity
• AI: Ryan/Andy to mold current discussion to a proposal

System Verilog Interfaces

• Solve simple bundles
• has a concurrent code region
  • use for assertions / monitors
  • testbench behavior

Record Closely Related

• Similar to closely related array types define built-in explicit type conversions (using type name)
• AI Ryan

Record Introspection

• May need new owner or additional owner as Chris is busy on other things

Multidimensional Array Restructuring

• Multidimensional Array to Single Dimensional Array
• Single Dimensional Array to Multi
• Who?

Generic Subprograms

• Specify generic in call of subprogram.
• Would be uniform wrt to generics on protected types.
• Would work as an alternative to an anonymous type on a subprogram.

Anonymous Types on Subprograms

• May be a burden on run-time. Require pass by reference.
• Trade off with generic subprograms - advantages? Lighter syntax

Next Meeting Date (proposed):

Thursday August 2, 8 am Pacific