P1076 Proposals and Requirements for VHDL-202x

This page contains the backlog from 1076-2019.

Do NOT create new items/entries in these tables.

All new proposals/requests are tracked through issues in GitLab repository IEEE-P1076/VHDL-Issues.


Active Proposals for VHDL-202x

If not clear, edit the table in RAW mode.

Status Values
*-DRAFT Proposal/LCS Underdevelopment. Comments Welcome
*-REVIEW Proposal/LCS call for comments
*-VOTE Proposal/LCS open for voting
*-APPROVED Proposal/LCS Approved. If Proposal, it's waiting for LCS
*-REJECTED Proposal/LCS Rejected


Repo Issue Proposal Status Who Description TBD
#100 Signal map aspect aka: SpaceShip . Bidirectional Connections Failed Patrick Lehmann Associate signals together using <=> Failed: LCS-2016-070 . LCS-2016-070a
#154 Map functions RAW Jim Lewis Create a function-like mapping between mode views  
#155 null mode for composite interface element actual /formal isolation Status Who Description LCS-2016-045b

General Language

Repo Issue Proposal Status Who Description TBD
#10 DPI Proposal Status PeterFlake Direct interface to other languages  
#103 Abstract Packages Status JimLewis Description TBD
#104 Configuration of Direct Instances Status RyanHinton Add a facility to write a configuration specification to control architecture selection possibly several hierarchy layers deep for a direct instantiation.  
#105 'access attribute to PT Status Who Description LCS-2016-014b
#106 Wait Level - Syntax Solution Updated for 202X Who Description  
#107 Signal Expressions in Signal Parameter Map Status Who Description LCS-2016-063
#108 Slicing Multidimensional Arrays Status RyanHinton Allow slice operations for more then 1 dimension.  
#109 Hierarchical Libraries Status PatrickLehmann LCS-2016-025 Allow a hierarchy of libraries in VHDL: protocol.packet.ethernet  
#110 Implicit Parameter and Port Connections Status JimLewis Shorthand notation for parameter and port maps  
#111 Add a method to determine if an output port is connected Status DaveG - StackOverflow Description  
#112 AssertApiExtension Status Who Extend Assert API to activate Call Path  
#113 Expressions in Bit String Literals - Dynamic Sizing Status Brent Hayhoe Adds the facility to define the bit width of the string literal with an integer expression. See alternative LCS-2016-072a
#114 Sequential Signal Declarations Status JimLewis Description  
#115 Composing Paths to External Names Status JimLewis Description  
#116 CrossLanguageInstances Status Who Related to DPI  
#117 Multiple Top-Level Designs Status CliffordWalinsky

Does this require a change? Does the LRM allow this now?

Only concerns are about paths in both external names and attributes: 'INSTANCE_NAME 'PATH_NAME

#102 Sequential declarations in "if", "case", or "loop" Status Who Description failed: LCS-2016-007a
#118 Allow work in context clause Status Who Potentially conflicts with LCS-2016-I07  
#119 Fix 2008 Context Clause Status Who Potentially conflicts with allow work in context clause LCS-2016-I07
#120 Aliases to Design Units - ie renaming packages Status PatrickLehmann Direct interface to other languages  
#121 Preponed Processes (clocks) Status JimLewis Execute in dedicated delta cycles before normal cycles begin - allows clock propagation - although for simple clock name association <=> will solve the issue  
#122 Process-All and Implicit Signals Status Brent Hayhoe Sensitivity = ALL + implicit items: signal'transaction  
#123 Extended String Literals Status JimLewis, DanielKho Support C Style String Literals  
#92 Read differences of bit_vector and std_logic_vector Status JimLewis Description TBD
#125 External Non-Shared Variable Name Status Brent Hayhoe Add the ability to reference local process variables and VHDL93 shared variables via the 'external name' syntax.  
#126 Deferred Shared Variables Status Who Description LCS-2016-080a
#127 Deferred Signals Status Brent Hayhoe Allow deferred signals in packages.  
#128 Extension to LCS 099 - intended to make more things locally static Status Who Description LCS-2016-099a
#129 Extra comma at the end of lists Status Who Description LCS-2016-071b
#130 Explore list of system env variables Status Who Need Use Case LCS-2016-006g
#131 Embedded FSM Language RAW Patrick Lehmann Add a state machine language.  
#132 Reflection API - Create values RAW Lieven Lemiengre, Patrick Lehmann Create and assign values from mirrors at runtime.  
#133 Relaxed OTHERS rules in aggregates Status RyanHinton Relax the rules for using OTHERS in array aggregates  
#134 Overload Assignment Operator Status Who Ability to overload the assignment operator := would be useful  
#135 Range constructor RAW Patrick Lehmann Allow x downto y to be used to create a range record instance.  
#136 Extended Ranges Status PatrickLehmann Make ranges more powerful see LCS-2016-099
#137 Extended user-defined attributes Status PatrickLehmann Let users define new attributes, which for example map to functions.  
#138 Subprogram attributes: actual, and formal - use model? Status Brent Hayhoe Access subtype information of actual port/parameters LCS-2016-060
#139 Generate Statement Alternate Path Names Status Who Description LCS-2016-I15 . LCS-2016-I15a - Dissenting opinion
#140 Process(all) sensitivity list Should Not Include Signals in All Reachable Subprograms Status Who Description LCS-2016-I18
#141 Wait with a repeat count Status JimLewis Description  
#142 define parameters for env.stop Status Who Define standard parameters for env.stop  
#143 Named Package Bodies Status JimLewis Description  
#144 Unique Condition - OrIf Status PeterFlake Description  


Repo Issue Proposal Who Description TBD
#145 Integers of arbitrary length MartinThompson Add integers of arbitrary length  
#146 Long Integers 64 bit type Who 64 bit integers LCS-2016-026
#147 Extended Integers DanielKho Require a minimum of 64 bits for integers.  
#148 Enhanced Integers JonasBaggett New derived integer types fittable for synthesis.  
#149 Physical Type Range KevinThibedeau Require that user-defined physical types can cover the same range as time.  
#150 Modular Integer Types MartinThompson Description  
#151 Implicit Conversions for Like Types Who Addresses issues with assigning integer literals to unsigned, signed, real literals to ufixed, sfixed, and float, and vice-versa. Obviously with some constraints.  
#152 Additional Operators to Integers Who Add Logic Operators for Integers LCS-2016-051
#153 Operations on integers Who Allow boolean and other operations on integers, that have a range as power of two.  

Types Enhancements

Repo Issue Proposal Status Who Description TBD
#156 Unions and/or Variant Records Status JimLewis Need unions to describe coverage that can either be a range or a single value  
#157 Records with discriminants RAW Patrick Lehmann Create typed unions.  
#158 Derived Scalar types RAW Jim Lewis, Patrick Lehmann Derive integer types (or every scalar type).  
#159 Derived enumerations RAW Patrick Lehmann Derive enumeration types.  
#160 Derived records RAW Patrick Lehmann Derive record types. See tagged records in SUAVE  
#171 Derived protected types RAW Patrick Lehmann Derive protected types.  
#101 Selected names for types implementation of external names for types Status Who Description failed: LCS-2016-028
#161 Anonymous types for external names implementation of external names for types 202X partial implemented Who Description failed: LCS-2016-028a
#162 Record Introspection Status ChrisHiggs Convert between a record and a vector LCS-2016-041
#163 Record Introspection & Indexing
Record Indexing
Status Brent Hayhoe Proposal to allow indexing and scanning of elements within record structures. MERGED (WAS: Member attribute for records) LCS-2016-069a
#164 Accessing record elements RAW Brent Hayhoe, Patrick Lehmann Allow handling of records similar to arrays.  
#165 Access to logical representation of VHDL objects Status JonasBaggett Access to binary representation of VHDL objects via new attributes  
#166 2 and 4 State values Status Who Derived / constrained type that automatically and can be controlled during simulation elaboration.  
#167 Clarify the Subtype of an Alias that refers to an Unconstrained Port Status Who Description  

Protected Types

Repo Issue Proposal Status Who Description TBD
#80 Protected Type initialization RAW Patrick Lehmann Add a protected type constructor. ?? Already have generics  
#168 Protected Types with Wait and Private Signals Status JimLewis Description TBD
#169 Protected Types with Public Signals Status JimLewis Description  
#170 Call a method of a protected type in a declaration Status JimLewis Description  

Language Regularization

Repo Issue Proposal Status Who Description TBD
#172 Consistent Package API RAW Lars Asplund Create a consistent API (mainly naming convention).  
#173 Package Name Case Sensitivity Status Who Description TBD

Overhead Tasks

Repo Issue Proposal Status Who Description TBD
#174 BNF Clean-up RAW Patrick Lehmann Clean-up BNF rules.  
#175 RequirementNumbers - Enumerate 1076 with requirement numbers. Status KenCampbell Description  

Testbenches / Continuous Integration

Repo Issue Proposal Status Who Description TBD
#176 Review testbenches RAW Lars Asplund and others Review existing testbenches.  
#177 New testbenches RAW Lars Asplund and others Add more testbenches.  


Repo Issue Proposal Status Who Description TBD
#85 DREAD, DWRITE, Integer D, H, O, B Read and Write Status NewPerson Description LCS-2016-006b
#178 Subsume IEEE Std. 1076.4 RAW Jim Lewis, Patrick Lehmann Reactivate IEEE Std. 1076.4 Timing (VITAL) as part of IEEE Std. 1076.  
#179 Updates to standard packages - split into LRM and Packages Status RyanHinton Additions to LRM, standard, std_logic_1164, numeric_std, math_real, math_complex, and fixed_pkg. Some may be redundant  
#180 Move definition of TEXT, INPUT, OUTPUT Status Who

Could have a context declaration that does:

Context IO is

use std.textio.text ;

use std.textio.OUTPUT;

use std.textio.INPUT;

end context;

#181 Stop Binary/Octal/Hex Read At Trailing Underscore Status CliffordWalinsky Test results from GitLab LRM already does this. Could be better written, but is correct and tests correct in simulations  
#182 Flag metavalues detected by ?? Status JimLewis Description  
#183 Real Matrix Math Package (and Vector) Status DavidBishop Matrix Math User's Guide (pdf)
Packages (zip)
  Updates to standard packages - split into LRM and Packages Status RyanHinton

Note this is listed here and in enhancements.

Additions to LRM, standard, std_logic_1164, numeric_std,
math_real, math_complex, and fixed_pkg

#184 Create natural_vector Status JimLewis Create natural_vector as a subtype of integer_vector  
#185 Update std_logic_arith Status JimLewis Update std_logic_arith to simplify interoperability with numeric_std  

VHDL AMS 1076.1 Proposals that go in 1076

Item Who Status Last Modified Description Status
Table Driven Modeling Joachim Haase et.al.
Forwarded to Open Source Group
5/24/2012 The package supports the description of functional dependencies y = f(x1, x2, ..., xn) based on a number of (n+1)-tupels (y, x1, x2, ..., xn). Emphasis is on floating point functions, and various interpolation schemes are supported. More details, and a reference implementation can be found in a protected area of the P1076.1 web. 202X

Change Proposals for IEEE Packages

Item Who Status LCS Link Rank Description Final Status
numeric_std, fixed and float bugs and consistency updates DavidBishop     3 Bug fixes and consistency updates for numeric_std,
fixed_generic_pkg.vhd, and float_generic_pkg.vhd
Ask David
Fixed point Algorithmic User's Guide (pdf) DavidBishop REVIEW     Package (zip) Open Source Doc
Floating point Algorithmic User's Guide (pdf) DavidBishop REVIEW     Package (zip) Open Source Doc

Someday Maybe Proposals

Repo Issue Item Who Status Rank Description Status
  VHPI Impact       VHDL-2008 & VHDL-2019 impact to VHPI Low Priority
  VHPI for PSL       PSL impact to VHPI Low
  Standard Instances of Float OPEN     Define standard instances of float_generic_pkg and fixed_generic_pkg Low
  Vector literal introspection JimLewis RFC 35 Distinguish between std_logic_vector and integer_vector literals Low
  Object Orientation     39 Links to different proposals Low
  Architecture Generic LarsJensen RFC 83 Implements architecture instantiation through generics Low
  Dynamic Process, Instances, Fork Join     91   Low
  Shorthand Subprogram Declarations JimLewis - 92 - Low
  Truth Tables Need Owner   98 Truth table for multi-input/multi-output Low
  Asynchronous Channels KevinCameron   100 Asynchronous channels (aka pipes) Low
#76 Clocked Shorthand DanielKho RFC 103

Shorthand to infer flip-flops and pipelining

Z <= A when rising_edge(Clk) ;

process(A, Clk)


if rising_edge(Clk) then

Z <= A ;

end if ;

end process ;

Z <= A when Sel = '1' else B ;

Open Source Group?
  Dynamic Rewiring KevinCameron   105 Allow runtime re-elaboration and re-wiring  
  Attribute Shorthand DanielKho RAW   Shorthand to create attributes.  

Rejected Proposals

Item Who Status Rank Description StatusPriority
Object Inspection JingPang RAW   Method to do introspection on names, find different objects and find all instance labels whose component is xyz. see VHPI
Use of Unicode MartinThompson Reject   Add unicode for strings, files, identifiers, comments 202X - Issue, UFT8 - How do we size strings - one character may require multiple multiple UTF8 characters. Current scope prevents multibyte issues. See python 3 when switched to unicode.

Items Subsumed by other items

Item Who Status Description Supporters Priority
Signal Pools KevinCameron     Ranking: 106 - Alternative to wire-like communication for RF  
User Defined IO Rules KevinCameron     Ranking: 107 - Move rules about in/out/inout to types  
Protected Type Updates JimLewis -   Numerous  

Proposals for 1076.6 - Requires a Chair for this activity

Requires separate working group and vendor participation.

This work would potentially be done by a separate working group. Requires a chair. JimLewis will help you through the IEEE process, but you will need to get vendor participation for the effort to be relevant.

Item Who Status Last Modified Description Supporters Priority
FSM Safe Design Brent Hayhoe RFC   Proposal to allow safe state identification for synthesis in FSM designs.  
Synthesis Attributes       Attributes for RAM, ROM, ... Define these in 1076?  
Assertions as Directives main.JimLewis     Support ZeroOneHot, ...  
Synthesizable 'event          
Support Synthesis of Reals DanielKho RAW   Simplify synthesis of floating-point operations, by using real to encapsulate synthesizable fixed- or floating-point types. Synthesis
Synthesizable Reports and Assertions DanielKho RFC 77

Allow assertions to count in synthesis

Emulator behavior

Reporting to the synthesis log? Check generic values are appropriate?

Compile time assertions?

Multicycle Path Specification     97 Speciification of multi-cycle paths in language syntax Synthesis
Specifying Timing Constraints DanielKho RAW   Allows RTL designers to specify timing constraints directly from HDL. Synthesis
Synthesizable 'event Attribute DanielKho RAW   Synthesize 'event for DDR FFs. Synthesis

Items to forward to open source package group

Item Who Status Last Modified Description Supporters Priority
File IO for RTL ROM JimLewis
Forwarded to Open Source Group
  Ranking: 24 - File IO for RTL ROM  
Functional Coverage JimLewis
Forwarded to Open Source Group
  Implemented by open source group OSVVM  
Random Stimulus JimLewis
Forwarded to Open Source Group
  Implemented by open source group OSVVM  
Extended Hardware Functions - RTL Macros  
Forwarded to Open Source Group
  RTL Macros. Meeting: Dec 15, 2011 and Mar 31, 2011  
Associative Arrays  
Forwarded to Open Source Group
  See TBV Propoal 2  
Queues / FIFO  
Forwarded to Open Source Group
  See TBV Proposal 4  
Sync and Handshaking  
Forwarded to Open Source Group
  See TBV Proposal 7  
Memory / Sparse array  
Forwarded to Open Source Group
  See TBV Proposal 12  
Loading and Dumping Memories  
Forwarded to Open Source Group
  See TBV Proposal 18  
Forwarded to Open Source Group
  See TBV Proposal 19  
Create open source boost/C++ like libraries       Meeting: Dec 15, 2011  
to_integer and to_integer_vector JimLewis -   -  
Graphics Library DanielKho
Forwarded to Open Source Group
  Implement a graphics library for VHDL.  
Regular Expressions DanielKho
Forwarded to Open Source Group
  Implement VHDL regular expressions.  

Raw Requirements Lists

List Description Notes
ISAC Active IR List    
Old Meeting Action Item List Current Action Items now tracked in meeting minutes  
Bugzilla List    
IEEE VHDL 2008 Subgroup Lists (TBV, FT, DTA, )    
Accellera VHDL 2008 Remaining Items List    
Raw Requirements in Text of Original Page    

Topic revision: r25 - 2021-05-16 - 16:02:22 - UnaiCorral
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