Extended Hardware functions like mux, decoders, adders

Proposal Editing Information

  • Who Updates:
  • Date Proposed:
  • Date Last Updated:
  • Priority:
  • Complexity:
  • Focus: Testbench

Requirement Summary

  • Simplify Creation of RTL macros (Also interested: MartinThompson, DanielKho):
  • Library of standard functions
    • Mux2, what else?
      • To what use, Jim says behavior, David K. suggests mixed level of abstraction, retargetting
  • Syntax based flip-flop extensions are here: ClockedShorthand

See also: Dec 15, 2011 and Mar 31, 2011


Recommend that we forward this to the open source package working group for implementation separate of the VHDL standard.

Create hardware with procedure and function calls. For example, use a procedure for a flip-flop:

Reg(Clk, D, Q) ;

RegPipe (Clk, D, Q, 5) ; -- adds a 5 deep pipelining / shift register.


Related and/or Competing Issues: None

Use Model:


General Comments

The open source and vendor independet IP core library PoC comes with several syntheziable functions.
Examples for one-liners:

  • a D-FF in standard VHDL
    mySignal_reg <= mySignal when rising_edge(Clock);
  • a D-FF with enable and reset, as well as a reset value (INIT)
    mySignal_reg <= ffdre(q => mySignal_reg, d => mySignal, en => enable, rst => reset, INIT => '1') when rising_edge(Clock);
  • an optional output register
    output <= output_i when registered(Clock, IS_REGISTERED);
  • Encoding conversion
    gray <= bin2gray(Counter);
    onehot <= bin2onehot(Counter);

Source: PoC.components and PoC.utils

-- PatrickLehmann - 2016-02-


Add your signature here to indicate your support for the proposal

-- MartinThompson - 2013-02-22

-- PatrickLehmann - 2016-02-19

Topic revision: r5 - 2020-02-17 - 15:34:30 - JimLewis
Copyright © 2008-2021 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback