Foreign / Cross Language Model Instances

Proposal Editing Information

  • Who Updates: .
  • Date Proposed:
  • Date Last Updated:
  • Priority:
  • Complexity:
  • Focus: Testbench

Requirement Summary

  • Env 1, 4: Foreign / Cross Language Model Instances
    • Type mapping per DPI proposal
    • Formalize what tools are already doing.
    • What types need to be exchanged between SV and VHDL?

Proposal

Rationale

Related and/or Competing Issues: None

Use Model:

Questions

General Comments

-- ErnstChristen - 2015-01-27

I don't see this as an issue to be addressed by VHDL.

Supporters

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Topic revision: r3 - 2020-02-17 - 15:34:29 - JimLewis
 
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