Mapping Expressions to Signal Parameters

Proposal Information

  • Current Owner: JimLewis, ...
  • Contributors: JimLewis, ...
  • Date Proposed: 2014-June-22
  • Date Last Updated: 2020-October-30
  • Priority:
  • Complexity:
  • Focus: Testbench
  • Related Issues: loosely, but both are useful [[WaitLevel] [Wait Level - Syntax Solution] ]
  • Competing Issues: None

Requirement Summary

Mapping Expressions to Signal Parameters.

One application is to provide a code based solution to Level Sensitive Wait

See also [[WaitLevel] [Wait Level - Syntax Solution] ]

A Code Solution

This can easily be accomplished with the code

if A /= Level then
  wait until A = Level ;
end if; 

However, what is being sought is a more concise solution.

Encapsulation with a Procedure

If the following worked, it would be an acceptable solution. However while a signal input to an entity allows expressions with VHDL-2008, a signal input to a parameter of a subprogram does not.

procedure WaitLevel (
  signal condition : in boolean 
) is 
begin
  if not condition then
    wait until condition ;
  end if ; 
end procedure WaitLevel ; 

General support issues: When an expression is passed as input signal parameter, it would have the default value of the type (here false) until a delta cycle passes. Here that works just fine.

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Topic revision: r1 - 2020-10-30 - 16:17:55 - JimLewis
 
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