Raw Requirements, Originally on Bottom of Page

Timing Information similar to SDC in VHDL

See proposal: TimingConstraints

  • include timing information in native VHDL. Similar to SDC, but in native VHDL. Probably with attributes? This was suggested by someone earlier.
    • We already have "time" and "after", perhaps we can use these to define timing constraints.

Standardise switch-level modelling

Need Proposal

  • Standardise switch-level modelling (there are already a few VHDL implementation models of MOSFETs available). -- DanielKho - 2011-07-01

Simulation Controls

See proposal: SimulationControls

  • Simulation Controls
    • In a hierarchy of tools, allowing foreign interface to control run time (as in verification)
    • class of capabilities, such as save and restore model image for known good state starting point
    • Simulation set up, exit
    • error/status reporting/exception handling (call back?)
    • PSL compatability

useful for cosimulation and system simulation driven externally or external stimulus and validation

Synthesizable Constructs -- DanielKho - 2011-06-29

Synthesis of Real

See proposal: SupportReal

  • Allow synthesis of reals. Underlying model can use the fixed or floating point packages.
    • Solutions already available with floating / fixed point packages, so they can be re-used as underlying models for real types.

Synthesis of 'event

See proposal SynthesizableEvent synthesisable 'event attribute for dual-edge triggers. Synthesis tools can infer DDR blocks or have a dual-edge trigger configuration using multiple flip-flops.

process(clk) is
    if clk'event then
        /* Output q is triggered at both edges of the clk. */
    end if;
end process;

Another example coding style for multi-clock FFs, refer slide 13 of <a target="_blank" href="http://www.synthworks.com/papers/vhdl_rtl_synthesis_1076_6_dvcon_2004_s.pdf">http://www.synthworks.com/papers/vhdl_rtl_synthesis_1076_6_dvcon_2004_s.pdf</a>

Synthesis of Report

See Proposal: SynthesizableReportsAssertions

  • synthesisable "report" and "assert" statements, with the use of a physical interface bus (such as a UART, etc.) to act similar to a simulation console (or simulation log file).

Package Updates

See proposal FixedFloatUpdates

  • Modify the "fixed_generic_pkg-body.vhdl" to correct errors -- DavidBishop - 2013-08-28
  • Modify the "float_generic_pkg-body.vhdl" to correct errors. -- DavidBishop - 2013-08-28

  • Proposal.txt: Instructions to fix bugs in "fixed_generic_pkg-body.vhdl", "float_generic_pkg-body.vhdl" and the fixed point documentaiton
Topic revision: r3 - 2020-02-17 - 15:34:37 - JimLewis
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