RobMasterWDecodeMuxEntityNull < P1076

P1076 Web>Vhdl2019CollectedRequirements>InterfaceAndBundleEnhancements>RobMasterWDecodeMuxEntityNull (2017-04-02, PatrickLehmann) (raw view)EditAttach
---+ Master, 4 slaves, Shared Decode and Mux block

%TOC%

---++ Introduction

Working through Rob's example using [[TopLCS2016_045][LCS 2016 45]] Port Views plus [[LCS2016_070][LCS 2016 70]] SpaceShip

Use case has 
   * One master 
   * 2 Slaves - unique address and data width
   * 2 Memory Models - unique address and data width
   * Entity for Decoder, and Multiplexing
   * Uses Null Port mode to resolve differences
   

---+++ BusPkg - defines the unconstrained system types
<pre>library IEEE ; 
  use ieee.std_logic_1164.all ;
  
package BusPkg is
  -- defines basic types and views for an unconstrained system 
 type BusType is
   record
      Sel           : Std_uLogic;
      Address       : unresolved_unsigned;
      Read_Write    : Std_uLogic;
      WriteData     : Std_uLogic_Vector;
      DataValid     : Std_uLogic;
      ReadData      : Std_uLogic_Vector;
   end record BusType;
   
 type BusArray is array (natural range <>) of BusArray;
   
 view MasterView of BusType is
      Sel           : out;
      Address       : out;
      Read_Write    : out;
      WriteData     : out;
      DataValid     : in;
      ReadData      : in;
end view MasterView;

alias SlaveView is MasterView'CONVERSE ;

view SlaveArrayView of BusArray is
      others : view SlaveView;
end view SlaveArrayView;

end package BusPkg ;
</pre>


---+++ SystemPkg - Defines the address and data ranges for each component in the system
<pre>library IEEE ; 
  use ieee.std_logic_1164.all ;

package SystemPkg is
  -- Defines the System Interfaces as designed
  subtpe SlaveArrayRange is integer range 1 to 4 ; 
  
  subtype MasterAddressRange is integer range 31 downto 0 ; 
  subtype MasterDataRange is integer range 31 downto 0 ; 
  subtype MasterIfType is BusType(
       Address(MasterAddressRange), 
       WriteData(MasterDataRange), 
       ReadData(MasterDataRange) 
  ) ;

  constant Slave1ID : integer := 1 ;
  subtype Slave1AddressRange is integer range 10 downto 0 ; 
  subtype Slave1DataRange is integer range 7 downto 0 ; 
  subtype Slave1Range is integer range ... ;  
  view Slave1AddressView of unresolved_unsigned is 
     Slave1AddressRange : in ;
     others             : null ; 
  end view Slave1AddressView ; 
  view Slave1WriteDataView of Std_uLogic_Vector is 
     Slave1DataRange : in ;
     others             : null ; 
  end view Slave1AddressView ; 
  alias Slave1ReadDataView is Slave1WriteDataView'CONVERSE;
  view Slave1View of BusType is 
      Sel           : in;
      Address       : view Slave1AddressView ; 
      Read_Write    : in;
      WriteData     : view Slave1WriteDataView;
      DataValid     : out;
      ReadData      : view Slave1ReadDataView;
  end view Slave1View;

  constant Slave2ID : integer := 2 ;
  subtype Slave2AddressRange is integer range 10 downto 0 ; 
  subtype Slave2DataRange is integer range 7 downto 0 ; 
  subtype Slave2IfType is BusType(
       Address(Slave2AddressRange), 
       WriteData(Slave2DataRange), 
       ReadData(Slave2DataRange) 
  ) ;
  subtype Slave2Range is integer range ... ;   
  view Slave2AddressView of unresolved_unsigned is 
     Slave2AddressRange : in ;
     others             : null ; 
  end view Slave2AddressView ; 
  view Slave2WriteDataView of Std_uLogic_Vector is 
     Slave2DataRange : in ;
     others             : null ; 
  end view Slave2AddressView ; 
  alias Slave2ReadDataView is Slave2WriteDataView'CONVERSE;
  view Slave2View of BusType is 
      Sel           : in;
      Address       : view Slave2AddressView ; 
      Read_Write    : in;
      WriteData     : view Slave2WriteDataView;
      DataValid     : out;
      ReadData      : view Slave2ReadDataView;
  end view Slave2View;

  constant Memory1ID : integer := 3 ;
  subtype Memory1AddressRange is integer range 31 downto 0 ; 
  subtype Memory1DataRange is integer range 31 downto 0 ; 
  subtype Memory1Range is integer range ... ;   
  view Memory1AddressView of unresolved_unsigned is 
     Memory1AddressRange : in ;
     others             : null ; 
  end view Memory1AddressView ; 
  view Memory1WriteDataView of Std_uLogic_Vector is 
     Memory1DataRange : in ;
     others             : null ; 
  end view Memory1AddressView ; 
  alias Memory1ReadDataView is Memory1WriteDataView'CONVERSE;
  view Memory1View of BusType is 
      Sel           : in;
      Address       : view Memory1AddressView ; 
      Read_Write    : in;
      WriteData     : view Memory1WriteDataView;
      DataValid     : out;
      ReadData      : view Memory1ReadDataView;
  end view Memory1View;

  constant Memory2ID : integer := 4 ;
  subtype Memory2AddressRange is integer range 31 downto 0 ; 
  subtype Memory2DataRange is integer range 31 downto 0 ; 
  subtype Memory2Range is integer range ... ;   
  view Memory2AddressView of unresolved_unsigned is 
     Memory2AddressRange : in ;
     others             : null ; 
  end view Memory2AddressView ; 
  view Memory2WriteDataView of Std_uLogic_Vector is 
     Memory2DataRange : in ;
     others             : null ; 
  end view Memory2AddressView ; 
  alias Memory2ReadDataView is Memory2WriteDataView'CONVERSE;
  view Memory2View of BusType is 
      Sel           : in;
      Address       : view Memory2AddressView ; 
      Read_Write    : in;
      WriteData     : view Memory2WriteDataView;
      DataValid     : out;
      ReadData      : view Memory2ReadDataView;
  end view Memory2View;

end package SystemPkg ;
</pre>


---+++ master_slave_exchange - Manages the details of connecting a master and slave
<pre>
library IEEE ; 
  use ieee.std_logic_1164.all ;
  use work.BusPkg.all ;

entity Decode_Mux is
  generic (SlaveID : integer ) ; 
  port (
      master : view MasterView'CONVERSE; 
      slave  : view SlaveArrayView'CONVERSE
  ) ;
end entity Decode_Mux ;
architecture exchange of Decode_Mux is 
begin
  process (...)
  being
    for i in 1 to 4 loop 
      slave(i).Address     <= master.Address;
      slave(i).Read_Write  <= master.Read_Write;
      slave(i).WriteData   <= master.WriteData;
    end loop ;
    
    case to_integer(Master.Address) is
      when Slave1Range =>
        slave(Slave1ID).Select    <= master.Select;
        master.DataValid   <= slave(Slave1ID).DataValid;
        master.ReadData    <= slave(Slave1ID).ReadData ;
        
      when Slave2Range =>
        slave(Slave2ID).Select    <= master.Select;
        master.DataValid   <= slave(Slave2ID).DataValid;
        master.ReadData    <= slave(Slave2ID).ReadData ;
    
      when Memory1Range =>
        slave(Memory1ID).Select      <= master.Select;
        master.DataValid     <= slave(Memory1ID).DataValid;
        master.ReadData      <= slave(Memory1ID).ReadData ;
        
      when Memory2Range =>
        slave(Memory2ID)Select      <= master.Select;
        master.DataValid    <= slave(Memory2ID).DataValid;
        master.ReadData     <= slave(Memory2ID).ReadData ;
    
      when others =>   null ; 
    end case ; 
  end process ; 
end architecture exchange ; 

end architecture exchange ;
</pre>

---+++ System Basic:  Connecting the Master and Slaves 
<pre>
library IEEE ; 
  use ieee.std_logic_1164.all ;
  use work.BusPkg.all ;
  use work.SystemPkg.all ;

entity system_basic is
  port (
    ..
  ) ;
end entity system_basic ;
architecture structural of system_basic is

  -- connections for the SPI intefaces 
  signal master_bus  :  BusType(
       Address(MasterAddressRange), 
       WriteData(MasterDataRange), 
       ReadData(MasterDataRange) );
  signal slave_array_bus  : BusArray(SlaveArrayRange)(
       Address(MasterAddressRange), 
       WriteData(MasterDataRange), 
       ReadData(MasterDataRange) ) ; 

  --  Components
  component Master  port (master_bus  : view MasterView; ...  ) ;
  component Slave1  port (slave_bus   : view Slave1View; ...  ) ;
  component Slave2  port (slave_bus   : view Slave1View; ...  ) ;
  component Memory1 port (memory_bus  : view Memory1View; ...  ) ;
  component Memory2 port (memory_bus  : view Memory2View; ...  ) ;
  
  component Decode_Mux is
    port (
      master : view MasterView'CONVERSE; 
      slave  : view SlaveArrayView'CONVERSE
    ) ;
  end compoenent Decode_Mux;

begin

  -- Master Instance 
  master_1 : Master (master_bus => master_bus, ... ) ;

  -- Decode Mux Instance 
  master_1 : Master (master => master_bus, slave => slave_array_bus ) ;
     
  -- Slave1 Instance 
  slave_1 : Slave1 (slave_bus => slave_array_bus(Slave1ID)) ; 
     
    -- Slave2 Instance 
  slave_2 : Slave2 (slave_bus => slave_array_bus(Slave2ID)) ;
     
  -- Memory1 Instance 
  slave_1 : Memory1 (slave_bus => slave_array_bus(Memory1ID)) ;
     
    -- Memory2 Instance 
  slave_2 : Memory2 (slave_bus => slave_array_bus(Memory2ID)) ;
     
end architecture structural ; 
</pre>
Topic revision: r2 - 2017-04-02 - 15:45:29 - PatrickLehmann
P1076