Interface and Bundle Enhancements

Proposal Details

  • Who Updates: P1076Group
  • Date Proposed: ongoing
  • Date Last Updated:
  • Priority:
  • Complexity:
  • Focus:

Current Situation

We have numerous requests for abstract connections between RTL components as well as testbench components. This proposal intends to extract a unified set of requirements and use modes.

Interface requirements documentation

Interface Semantics Discussion

Updated Use Cases

  1. SPI implemented with LCS 45 Port View + LCS 70 SpaceShip

Bus Master, 4 Slaves with Different Address and Data lengths

  1. Rob Style: Bus with Decode and Mux in Separate entity + separate slave busses
  2. Brent Style: Decode/Mux in Master. Using Entities and Spaceships
  3. Rob Style: Bus with Decode and Mux in Separate entity + 1 general purpose slave bus - using map
  4. Rob Style: Bus with Decode and Mux in Separate entity + 1 general purpose slave bus - using NULL LCS 45 b
  5. Brent Style: Decode/Mux in Master Using Generics - Brent's Code

Updated Use Cases that look forward

  1. SPI Beyond Current LCS'

Use Cases

  1. Interface,doc 3.1.: Transaction Based Testbench
  2. Interface.doc 3.2.: RTL Bundles
  3. Interface.doc 3.2.: RTL Simple Interface
  4. Interface.doc 4.0.: Current Capabilities
  5. Interface.doc 5.0.: Implementation Considerations
  6. Interface.doc 6.0.: Interface Implementation
  7. Interface.doc 7.0.: Historical Discussion
  8. Proposal: Records with Directional Subtypes
  9. Proposal: "Bus" port mode for bidirectional port signals
  10. Proposal: Interface Construct and Port Mode Configurations
  11. Proposal: Packages as an Interface Construct
    Simulatable example of generic package as interface
    Simulatable example of regular package as interface with internal record signal - does not use generic pacakges
  12. IR2067: Logical link interface abstraction
  13. IR2089: Directional Records
  14. VHDL-200x FT17: Composite interface mode
  15. Use Case: Minimal RTL Signal Based Interface
  16. Use Case: Complex RTL Signal Based CPU Bus Interface
    Compressed tarball with VHDL files
  17. SPI Example
    Compressed tarball with VHDL files
    Simple SPI simulation model using record signal in package (emulating the interface)

Requirements

  1. RTL Requirements- Light Weight -
    1. Must be synthesis capable
    2. Composite/Collection of objects
      • signal - required
    3. Create by declation, instantiation, ...
    4. Method to access elements/subelements that is independent of method or location of declaration
    5. Declare / specify on entity interface or subprogram interface
    6. Associate/Map on entity instance or subprogram call
    7. ?Generics
    8. Method for sizing unconstrained elements
    9. ?Support Shared Globals (Clk, Reset, ...) - similar to SV interfaces
      1. How do we handle globals like clk and reset? How does this impact events?
    10. Events - do we care whether events are on individual objects or as a composite
      1. What does event mean if the object is out mode?
      2. What about a collection of clocks?
      3. What about a collection of busses?
    11. Assignment to entire collection? TBD
      1. What if modes/directions are not all out or inout
      2. Would need use cases to validate if all out or inout is useful
      3. ?No because then a record could be used instead
    12. Composition
      1. Collecting other collections
      2. Collecting other modes
      3. ?Shared Globals (Clk, reset, ...)
    13. Access Control / Decomposition - similar to ModPort
      1. Direction control of objects
      2. support conjugate and monitor (all in) capability (via attribute or other)
      3. ?Shared Globals (Clk, reset, ...)
      4. ??Access to Subprograms
      5. ??Exclusion of objects
      6. Must support a access control/Decomposition declaration/specification
      7. ?Can access control happen directly on interface?
    14. Decomposition within a program (architecture / procedure)
      1. Assign to items of the collection
      2. Read individual items of the collection
    15. ??Subprograms
  2. Behavioral Requirements
    1. Composite/Collection of objects
      • signal - required
      • shared variable - required (???regular variables???)
      • constant - ???
      • file - ???
      • terminal - required - (VHDL-AMS)
      • quantity - required - (VHDL-AMS)
      • bundle - required
    2. Create by declation, instantiation, ...
    3. Method to access elements/subelements that is independent of method or location of declaration
    4. Declare / specify on entity interface or subprogram interface
    5. Associate/Map on entity instance or subprogram call
    6. Support Generics
    7. Method for sizing unconstrained elements
    8. Support Shared Globals (Clk, Reset, ...) - similar to SV interfaces
      1. How to handle globals like clk and reset?
    9. Events - want events on individual objects
      1. What does event mean if the object is out mode?
      2. What about a collection of clocks?
      3. What about a collection of busses?
    10. Assignment? Only to elements within the collection
    11. Composition
      1. Collecting other collections
      2. Collecting other modes
      3. Shared Globals
    12. Access Control / Decomposition - similar to ModPort
      1. Directions of objects
      2. support conjugate and monitor (all in) capability (via attribute or other)
      3. ?Shared Globals (Clk, reset, ...)
      4. ?Access to Subprograms
      5. ???Import/Export of subprograms - big change -
        1. impure subprograms need to access ports of a local entity
      6. Exclusion of objects
      7. Must support a access control/Decomposition declaration/specification
      8. ?Can access control happen directly on interface?
    13. Decomposition within a program (architecture / procedure)
      1. Assign to items of the collection
      2. Read individual items of the collection
    14. Subprograms
      1. access interface internals
    15. Avoid compiler issues when integrating
      port ( A : MyMode MyType) ; -- VHDL already has this in some areas.
      port ( A : <MyMode> MyType) ; -- A fix, but there are many variations
      port ( A : MyType(MyMode)) ; -- A fix, but there are many variations
    16. Internal to a model, use an identifier to dynamically associate with one of 2 identical interfaces
    17. Virtual Interface
      1. Change interface instance
      2. Dynamically plug in a different testbench

Active Proposals

  1. Use Case: Complex RTL Signal Based CPU Bus Interface
    Compressed tarball with VHDL files
  2. SPI Example
    Compressed tarball with VHDL files
  3. Port groups proposal (deprecated)
  4. Proposal: Packages as an Interface Construct
    Simulatable example of generic package as interface
    Simulatable example of regular package as interface with internal record signal - does not use generic pacakges
  5. Heterogeneous Interfaces
  6. Bundles proposal
  7. The Bundle as an Object Alternative
  8. Port views

Older Whiteboard Stuff

Old Whiteboards for brainstorming Proposals & Requirements

Implementation Candidates

Analysis of creating an interface capability based on record types

Arguments FOR

Arguments AGAINST

General Comments

Reference Links

Ernst's Proposal Related Documents

Brent Summaries:

Proposals:

Item Who Status Last Modified Description Supporters Priority
Interfaces: Attributes for Interfaces JohnAasen     Provide attributes for common derived interfaces  
Interfaces: Records with Directional Subtypes PeterFlake        
Interfaces: Packages as an Interface Construct JimLewis        
Interface Construct and Port Mode Configurations Brent Hayhoe RFC   Define a new Interface construct for use with composite types and a new Port Mode Configuration concept to provide customizable and hierarchical port modes  
Interfaces: Add "Bus" mode for bidirectional port signals BrianDrummond RFC   "Bus" mode on a record port allows different direction for each record member  
Interfaces: Heterogeneous Interfaces in VHDL ErnstChristen RFC 2015-11-05 Define an interface concept as a collection of objects. This makes it possible to give each signal element of an interface different modes without breaking backward compatibility. A port view concept allows a subset of an interface to be made available in a design unit.  

Documents:

Email threads:

Supporters

Add your signature here to indicate your support for the proposal

Comments

These points are what I expect from this proposal (as a minimum) in order to support RTL design implementation:

  • At present (VHDL 2008), an interface bus can be encapsulated in a single VHDL object of class signal or variable associated with a composite type(s).
  • Missing is the ability to pass this VHDL object as a single port/parameter association through the interface of an entity, and/or a component, and/or a block, and/or a procedure:
    • This can be achieved using the proposed new directional constructs of record/array view, port view, or mode view.
    • These new constructs, as well as defining the interface mode on an element by element basis, must have the ability to explicitly declare an element as disconnected functionally across the port/parameter interface whilst maintaining the composite subtype structure. This can be achieved using the proposed new mode type of null.
      • The actual of a port/parameter interface element of mode null has no driver or initial value for the connected object.
      • The formal of a port/parameter interface element of mode null cannot be read (unless it has an initial value associated with it) or driven and it is an error if otherwise attempted.
      • The purpose of a port/parameter interface element of mode null is to explicitly show the functional disconnection of the element from its composite port/ parameter interface.
    • These disconnected elements also require the ability to be controlled via generic constants as part of the new view construct.

-- Brent Hayhoe - 2016-09-20

Topic attachments
I Attachment Action Size Date Who Comment
Unknown file formatgz ComplexRTL.tar.gz manage 4.4 K 2015-10-16 - 00:23 ErnstChristen Code related to Complex RTL use case
Unknown file formatgz SPI_Bus.tar.gz manage 3.4 K 2015-10-16 - 00:22 ErnstChristen Code related to SPI bus use case
Compressed Zip archivezip SimpleSpi.zip manage 4.9 K 2015-10-22 - 05:56 JimLewis Simple SPI inteface using record signal in package
Compressed Zip archivezip package_as_interface.zip manage 11.1 K 2015-10-22 - 01:20 JimLewis Simulatable example for package as inteface
Compressed Zip archivezip package_record_as_interface.zip manage 11.6 K 2015-10-22 - 01:50 JimLewis Simulatable example for package with record signals as inteface
Topic revision: r26 - 2020-02-17 - 15:34:34 - JimLewis
 
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