Brent Master Multiplexer with Multiple slaves

Introduction

Working through the Brent's Master with Multiplexer Example LCS 2016 45 Port Views plus LCS 2016 70 SpaceShip

Use case has

• One master
• 2 Slaves - unique address and data width
• 2 Memory Models - unique address and data width

BusPkg - defines the unconstrained system types

library IEEE ; 
  use ieee.std_logic_1164.all ;
  
package BusPkg is
  -- defines basic types and views for an unconstrained system 
  type MasterWriteType is
     record
        Address       : Std_uLogic_Vector;
        Read_Write    : Std_uLogic;
        WriteData     : Std_uLogic_Vector;
     end record MasterWriteType;
     
  view MasterWriteView of MasterWriteType is
      Address       : out;
      Read_Write    : out;
      WriteData     : out;
  end view MasterWriteView;

  type SlaveResponseType is
     record
        Select    : Std_uLogic;
        DataValid : Std_uLogic;
        ReadData  : Std_uLogic_Vector;
     end record SlaveResponseType;
     
  type SlaveResponseArray is array (Natural range <>) of SlaveResponseType;

  view SlaveResponseView of SlaveResponseType is
     Select    : in;
     DataValid : out;
     ReadData  : out;
  end view SlaveResponseView;
  
  -- Master Interface
  type MasterType is
     record
        MassterWrite  : MasterWriteType ;
        SlaveResponse : SlaveResponseArray;
     end record MasterType;

  alias MasterResponseView is SlaveResponseView'CONVERSE; 

  view MasterArrayView of SlaveResponseArray is
     others : view MasterResponseView;
  end view MasterArrayView;

  view MasterBusView of MasterType is
      MasterWrite   : view MasterWriteView;
      SlaveResponse : view MasterArrayView;
  end view MasterBusView;

  -- Slave Interface
  type SlaveType is
     record
        MassterWrite  : MasterWriteType;
        SlaveResponse : SlaveResponseType;
     end record SlaveType;
     
  view SlaveBusView of SlaveType is
      MasterWrite   : view MasterWriteView;'CONVERSE
      SlaveResponse : view SlaveResponseView;
  end view SlaveBusView;

end package BusPkg ;

master_slave_exchange - Manages the details of connecting a master and slave

library IEEE ; 
  use ieee.std_logic_1164.all ;
  use work.BusPkg.all ;

entity master_slave_exchange is
  generic (SlaveID : integer ) ; 
  port (
    master : view MasterBusView'CONVERSE; 
    slave  : view SlaveBusView'CONVERSE
  ) ;
end entity master_slave_exchange ;
architecture exchange of master_slave_exchange is 
begin
  slave.WriteData.Address       <=> master.WrteData.Address(Slave.WriteData.Address'range);
  slave.WriteData.Read_Write    <=> master.WrteData.Read_Write;
  slave.WriteData.WriteData     <=> master.WrteData.WriteData(Slave.WriteData.WriteData'range);
  slave.SlaveResponse.Select    <=> master.SlaveResponse(SlaveID).Select;
  slave.SlaveResponse.DataValid <=> master.SlaveResponse(SlaveID).DataValid;
  slave.SlaveResponse.ReadData  <=> master.SlaveResponse(SlaveID).ReadData(Slave.ReadData.ReadData'range);
end architecture exchange ;

SystemPkg - Defines the address and data ranges for each component in the system

library IEEE ; 
  use ieee.std_logic_1164.all ;

package SystemPkg is
  -- Defines the System Interfaces as designed
  subtpe SlaveArrayRange is integer range 1 to 4 ; 
  
  subtype MasterAddressRange is integer range 31 downto 0 ; 
  subtype MasterDataRange is integer range 31 downto 0 ; 
  subtype MasterIfType is MasterType(
       MasterWrite(Address(MasterAddressRange), WriteData(MasterDataRange)),
       SlaveResponse(SlaveArrayRange)(MasterDataRange)) ;
  
  constant Slave1ID : integer := 1 ;
  subtype Slave1AddressRange is integer range 10 downto 0 ; 
  subtype Slave1DataRange is integer range 7 downto 0 ; 
  subtype Slave1IfType is SlaveType(
       MasterWrite(Address(Slave1AddressRange), WriteData(Slave1DataRange)),
       SlaveResponse(Slave1DataRange)) ;

  constant Slave2ID : integer := 2 ;
  subtype Slave2AddressRange is integer range 10 downto 0 ; 
  subtype Slave2DataRange is integer range 7 downto 0 ; 
  subtype Slave2IfType is SlaveType(
       MasterWrite(Address(Slave2AddressRange), WriteData(Slave2DataRange)),
       SlaveResponse(Slave2DataRange)) ;
  
  constant Memory1ID : integer := 3 ;
  subtype Memory1AddressRange is integer range 31 downto 0 ; 
  subtype Memory1DataRange is integer range 31 downto 0 ; 
  subtype Memory1IfType is SlaveType(
       MasterWrite(Address(Memory1AddressRange), WriteData(Memory1DataRange)),
       SlaveResponse(Memory1DataRange)) ;

  constant Memory2ID : integer := 4 ;
  subtype Memory2AddressRange is integer range 31 downto 0 ; 
  subtype Memory2DataRange is integer range 31 downto 0 ; 
  subtype Memory2IfType is SlaveType(
       MasterWrite(Address(Memory2AddressRange), WriteData(Memory2DataRange)),
       SlaveResponse(Memory2DataRange)) ;

end package SystemPkg ;

System Basic: Connecting the Master and Slaves

library IEEE ; 
  use ieee.std_logic_1164.all ;
  use work.BusPkg.all ;
  use work.SystemPkg.all ;

entity system_basic is
  port (
    ..
  ) ;
end entity system_basic ;
architecture structural of system_basic is

  -- connections for the SPI intefaces 
  signal master_bus  : MasterIfType;
  signal Slave1_bus  : Slave1IfType;
  signal Slave2_bus  : Slave2IfType;
  signal Memory1_bus : Memory1IfType;
  signal Memory2_bus : Memory2IfType;

  -- SPI Components
  component Master  port (master_bus : view MasterIfType; ...  ) ;
  component Slave1  port (slave_bus  : view Slave1IfType; ...  ) ;
  component Slave2  port (slave_bus  : view Slave1IfType; ...  ) ;
  component Memory1 port (memory_bus  : view Memory1IfType; ...  ) ;
  component Memory2 port (memory_bus  : view Memory2IfType; ...  ) ;
  
  component master_slave_exchange is
    generic (SlaveID : integer ); 
    port (
      master : view MasterBusView'CONVERSE; 
      slave  : view SlaveBusView'CONVERSE
    ) ;
  end compoenent master_slave_exchange;

begin

  -- Master Instance 
  master_1 : Master (master_bus => master_bus, ... ) ;

  -- Connect Slave1 Bus to Master
  master_slave_exchange_1 : master_slave_exchange
     generic map (SlaveID => Slave1ID)
     port map (
       master => master_bus,
       slave  => Slave1_bus
     ) ;
     
  -- Slave1 Instance 
  slave_1 : Slave1 port map (slave_bus => slave1_bus, ... ) ;
  
  -- Connect Slave2 Bus to Master
  master_slave_exchange_1 : master_slave_exchange
     generic map (SlaveID => Slave2ID)
     port map (
       master => master_bus,
       slave  => Slave2_bus
     ) ;
     
  -- Slave2 Instance 
  slave_2 : Slave2 (slave_bus => slave2_bus, ... ) ;

  -- Connect Memory1 Bus to Master
  master_slave_exchange_1 : master_slave_exchange
     generic map (SlaveID => Memory1ID)
     port map (
       master => master_bus,
       slave  => Memory1_bus
     ) ;
     
  -- Memory1 Instance 
  memory_1 : Memory1 port map (memory_bus => memory1_bus, ... ) ;


  -- Connect Memory2 Bus to Master
  master_slave_exchange_1 : master_slave_exchange
     generic map (SlaveID => Memory2ID)
     port map (
       master => master_bus,
       slave  => Memory2_bus
     ) ;

  -- Memory2 Instance 
  memory_2 : Memory2 port map (memory_bus => memory2_bus, ... ) ;
     
end architecture structural ;