package util is
   type logger is protected
      procedure log(msg : string; sev : severity_level);
   end protected;
end package;

library ieee;
   use ieee.std_logic_1164.all;

   use work.util.logger;

package factory is
   generic(
      type tpe;
      generic1 : natural;
      generic2 : string
   );
   shared variable foo : logger;

   type bus_rec is record
      clk : std_logic;
      rst : std_logic;
      element1 : tpe;
      element2 : std_logic;
      element3 : std_logic_vector(generic1 downto 0);
   end record;

   type bus_rec_arr is array (natural range <>) of bus_rec;

   port view master of bus_rec is -- port view or port bus?
      element1 => in;
      element2 => out;
   end port view master;

   port view slave of bus_rec is
      element1 => out;
      element2 => in;
   end port view master;

end package;

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;

entity e_sub is
   generic(
      package f is new work.factory generic map(<>)
   );
   port(
      bus_r : f.master for f.bus_rec;
      bus_r_slaves : /*  */ f.bus_rec_arr
   );
end;

library ieee; 
   use ieee.std_logic_1164.all;

entity e is
   generic(
      package f is new work.factory generic map(<>)
   );
   port(
      bus_r : /*  */ f.bus_rec;
      bus_r_slaves : /*  */ f.bus_rec_arr
   );
end entity e;

architecture RTL of e is
begin
   e_sub_inst : entity work.e_sub
   generic map(f => f)
   port map(
      bus_r => bus_r,
      bus_r_slaves => bus_r_slaves
   );
end architecture RTL;

library ieee;
   use ieee.std_logic_1164.all;

entity top is
end entity;

architecture RTL of top is
   package factory is new work.factory generic map (
      tpe => integer,
      generic1 => 10,
      generic2 => "foobar"
   );
 
   use factory.all;

   signal clk, rst : std_logic;
   signal clk2 : std_logic;
   signal m : bus_rec;
 
   port master_bus : bus_rec; -- master or slave modifier not required?
   port slave_busses : bus_rec_arr(0 to 10);
begin
 
   --------------------------------------------------------------------------
   -- Association operations: How do these signals/ports connect?
 
   -- Option 1: Can we dynamically reassociate signals to one another?
   clk2 <=> clk;
   m.clk <=> clk ; 
 
   -- Option 2: How about a port map to associate true signals to the port
   master_bus_inst : /* view */ master_bus port map (
      clk => rst,
      rst => rst,
      others => new
    )
 
      -- Option 3: Hybrid, a mapping operator but the port is still different
      -- than a signal.
      master_bus <=> m;
      master_bus <=> (
      clk => rst,
      rst => rst,
      others => new
   );
   --------------------------------------------------------------------------
 
 
   lbl : for i in 0 to 10 generate
      slave_bus_inst : slave_busses(i) port map (
         clk => clk,
         rst => rst,
         others => new
         -- elementx => master_bus.foo ???
      )
   end generate lbl;
 
   e_inst : entity work.e
      generic map(
         f => factory
      );
      port map(
         bus_r => master_bus,
         bus_r_slaves => slave_busses
      );
end architecture RTL;
 
--------------------------------------------------------------------------
-- This is more discussion of association, not necessarily directly
-- relating to interfaces.
entity clk_extractor is
   port ( WB_SYS : in t_wb_sys; o : out std_logic);
end entity clk_extractor;

architecture Behavioral of clk_extractor is
   port internal : std_logic;
begin
   internal <=> WB_SYS.CLK_I;
   internal <=> o;
end architecture Behavioral;

entity model is 
   port (A : bus1 ; B : bus1 ; ...) ;
end entity model ; 

architecture behav of model is 
begin
   I <=> A