Examples for Partially Connected Vectors on Port Map Proposal

The following would be legal, whereas it is currently not.

signal not_so_long_vector : std_logic_vector(15 downto 0);

component Some_Device is
    port (
        long_port : std_logic_vector(31 downto 0)
    );
end component Some_Device;

U1 : Some_Device port map( 
    long_port(15 downto 0) => not_so_long_vector, 
    long_port(31 downto 16) => open
);

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