LCS2016_001_Examples < P1076

P1076 Web>VHDL2017>LCS2016_001>LCS2016_001_Examples (2017-05-03, RobGaddi) (raw view)EditAttach

---+ Examples for Partially Connected Vectors on Port Map Proposal

The following would be legal, whereas it is currently not.

<sticky><verbatim>
signal not_so_long_vector : std_logic_vector(15 downto 0);

component Some_Device is
    port (
        long_port : std_logic_vector(31 downto 0)
    );
end component Some_Device;

U1 : Some_Device port map( 
    long_port(15 downto 0) => not_so_long_vector, 
    long_port(31 downto 16) => open
);
</verbatim></sticky>

---++ Comments

%COMMENT%

Topic revision: r1 - 2017-05-03 - 04:28:38 - RobGaddi

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