RGGBackground < VerilogAMS

VerilogAMS Web>AmsAssertions>RequirementsGatheringGroup>RGGBackground (2010-04-26, ScottLittle) (raw view)EditAttach

---++ Background on group members for RGG

This page can be used to quickly find background of group members and direct relevant questions to them for a detailed discussion.

---+++ Himyanshu Anand

RTL-Circuit equivalence checking, symbolic simulation, AMS assertions.

---+++ Kenneth Bakalar

---+++ Prabal Bhattacharya

---+++ Achim Bauer

Analog/mixed-signal system design, implementation and validation.
Creation of VAMS-models and verification environments.

---+++ Eduard Cerny

Digital assertions: specification, implementation (simulation and in the past formal), methodology, checker development, applications.

---+++ Scott Cranston

---+++ Mike Demler

Extensive experience in AMS design, author of *[[http://www.amazon.com/High-Speed-Analog-Digital-Conversion-Michael/dp/0122090489/ref=sr_1_1?ie=UTF8&s=books&qid=1235448067&sr=8-1][ _High Speed Analog to Digital Conversion_ ]]* (1991). Architect of Antrim Mixed-Signal Synthesis system. Group Director at Cadence - responsible for AMS reference flow. Senior Product Marketing Manager for HSIM at Nassda/Synopsys. Developed strategy for extending VMM to AMS. Author of the blogs [[http://synopsysoc.org/analoginsights/][ __Analog Insights__ ]] and [[http://the-world-is-analog.blogspot.com/][ __The World is Analog__ ]].

---+++ Surrendra Dudani

---+++ John Havlicek

---+++ Kevin Jones (RGG Leader)

---+++ Scott Little

---+++ Jim Lear

---+++ David Sharrit

-- Main.AnandHimyanshu - 04 Feb 2009

Topic revision: r6 - 2010-04-26 - 15:44:35 - ScottLittle

VerilogAMS