Summary

The AMS assertions committee is a subcommittee of the Accellera Verilog-AMS Technical Subcommittee. The charter of this committee is to study language features necessary for AMS assertions.

Recent Status

Meeting reminders, agendas, and minutes are sent to the ASVA mailing list. To receive this information please sign up for the ASVA mailing list as described below. Currently, the regular meeting is scheduled for Tuesdays at 9:30 a.m. CDT (GMT-05:00).

Call in details:

• Austria 0800291873
• Germany 08001014519
• India 0008006501482
• Israel 1809459738
• United States 8008671147

Participant code: 2324495

Current Focus

The committee currently has two areas of focus.

1. Previously we focused on developing a syntax and semantics for realtime sequences and properties that intermingle seamlessly with the current digital SVAs. We have encountered a number of problems with this work, and it has been deferred. Our current focus is on adding untimed LTL operators to SVAs. We are assuming that the SVAs will be checked by a digital simulator and as such can assume a discrete notion of time. In the future, we expect there will be a need for an assertion language that supports dense time, but we have chosen to focus on a simpler problem for the immediate future.

2. The addition of SVAs to Verilog-AMS. There is value from using assertions within Verilog-AMS models. We are exploring the necessary changes to Verilog-AMS to add the current

ASVA mailing list

To subscribe to the ASVA mailing list send an e-mail with a blank subject and body to asva-subscribe@listsNOSPAM.accellera.org.

ASVA mailing list archive

AMS Assertions Discussion Documents

Official Verilog-AMS site is here

Documents released to the sub-committee discussing Analog System Verilog Assertions will be posted here. Some of the documents will reside in the main repository hosted at eda.org for Verilog-AMS in the folder AMS Assertions

The documents released to the committee till now are as follows -

• Analog assertions proposal by Freescale Semiconductor can be found here.
• Some example analog properties provided by Freescale Semiconductor can be found here.
• "Timed Regular Expressions" by Asarin et al. can be found here.
• "A Kleene Theorem for Time Automata" by Asarin et al. can be found here.
• "Instrumenting AMS Assertion Verification on Commercial Platforms" by Mukhopadhyay et al. (IIT Kharagpur) can be found here.
• Analog and real time extension of System Verilog Assertions by Ed Cerny can be found here.
• Mike Demler's presentation on AMS assertions can be found here.
• Examples of analog assertions by Dejan, et al. can be found here.
• Example renderings of AMS properties in an SVA like syntax released by Freescale Semiconductor can be found here. The file has also been uploaded at this site as an attachment.
• Draft of a semantic preserving syntactic map from STL/PSL to an SVA like syntax (version 1.0) provided by Freescale Semiconductor can be found in the attached list of documents.
• Pseudo PSL/STL renderings of Freescale assertions by Dejan Nickovic can be found in the list of attached documents.
• Verilog AMS extensions for assertion support are listed here.
• Dejan Nickovic's thesis can be found here.

Requirements Gathering Group (RGG)

Requirements gathering group collected and defined the requirements considered essential for analog assertions. Details about RequirementsGatheringGroup

List of attached documents

• fslASVApropertyRenderings_1.01.pdf: Example renderings of AMS properties in an SVA like syntax provided by Freescale Semiconductor
• stlPslSyntacticMapToASVA_1.0.pdf: Draft of a semantic preserving syntactic map from STL/PSL to an SVA-like syntax
• freescale-assertions-stlpsl.pdf: Freescale Assertions - Renderings in Pseudo-STL/PSL Syntax by Dejan Nickovic
• 2009-03-30_Alternative_to_Assertions_Proposal.pdf: Transaction Layer Proposal by James Lear

-- ScottLittle - 2010-02-18