Requirements Gathering Group (RGG) Team (ordered alphabetically by last name)
  • Himyanshu Anand - Freescale, RTL-Circuit equivalence checking, AMS assertions
  • Kenneth Bakalar
  • Prabal Bhattacharya
  • Achim Bauer - exl-modeling, AMS modeling and verification
  • Eduard Cerny - Synopsys, Assertions, VCS simulator
  • Scott Cranston - Cadence, NC Simulator, Digital Simulation
  • Mike Demler
  • Surrendra Dudani
  • John Havlicek
  • Kevin Jones (RGG Leader) - Green Plug, AMS verification, languages, tools, formal methods
  • Jim Lear
  • Scott Little - Freescale, Formal methods, AMS verification
  • David Sharrit
  • Background of requirements gathering group members.

If you wish to join the RGG team please send a mail to verilog-ams, At, eda DOT, org with the subject "Analog Assertions RGG"


  • Requirements template by Kevin Jones is uploaded below.
  • Working draft of requirements document.
  • Proposal for extending SV bind.

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Meeting Minutes

-- ScottLittle - 2010-05-05

I Attachment Action Size Date Who Comment
PDFpdf AnalogSimulationInteraction_Dejan.pdf manage 39.7 K 2009-07-29 - 14:12 AnandHimyanshu Assertion Based Simulation Control of Analog Simulator - Dejan Nickovic
PDFpdf Analog_Assertion_Sampling_Requirements.pdf manage 222.5 K 2009-07-28 - 17:37 JimLear Description of the type of sampling of analog quantities needed for analog assertions.
PDFpdf RequirementsDraft_KevinJones.pdf manage 31.0 K 2009-02-02 - 21:45 AnandHimyanshu Requirements (Draft) by Kevin Jones
PDFpdf bindProposal.pdf manage 46.3 K 2009-05-20 - 23:29 ScottLittle Ideas about SV/VAMS interoperability for assertions.
Texttxt outline-2010-07-14.txt manage 2.5 K 2010-07-15 - 21:14 ScottLittle Outline of remaining assertions tasks.
PDFpdf semantics.pdf manage 194.5 K 2010-07-15 - 21:06 ScottLittle Some Notes on Realtime Semantics
Texttxt seq_prop_interaction.txt manage 5.6 K 2010-07-15 - 21:08 ScottLittle Notes on realtime sequence and property interaction
Topic revision: r56 - 2010-07-15 - 21:14:12 - ScottLittle
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