MeetingMinutes20091014 < VerilogAMS

VerilogAMS Web>AmsAssertions>RequirementsGatheringGroup>MeetingMinutes20091014 (2009-11-03, AnandHimyanshu) (raw view)EditAttach
Attendees:<br /><br />00000000000000010000101111000000000 Qamar Alam<br />11111111111111111110101111111011111 Himyanshu Anand<br />01111111100111111011101000111111111 Kenneth Bakalar<br />11111010101101101110110000111000111 Prabal Bhattacharya<br />00000000000000110000101001000010010 Sri Chandra<br />01111011111111111101101011111011111 Eduard Cerny<br />11101110000101101011101111101111111 Scott Cranston<br />00000000000000010000000000000001000 Dave Cronauer<br />00000000000011000000000111111001111 Dejan Nickovic<br />11011101111001000000000000000000000 Mike Demler<br />00000000000000000000000000000000000 Surrendra Dudani<br />11100000001111111111110011011111111 John Havlicek<br />11100011001000000000000000000000000 Kevin Jones (RGG Leader)<br />00000001111111111011101111111111111 Jim Lear<br />00000000000011101110000000000000000 Top Lertpanyavit<br />11111101101111111111111110111111111 Scott Little<br />00000000000001000000000000000000000 Erik Seligman<br />10100000000000000000000000000000000 David Sharrit<br />00000001000000000000000000000000000 Murtaza<br />00000001000000000001011001100000010 Martin O'Leary
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Decisions:
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Action Items:
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Details:

JL: When you sample, it does not force a time point.

KB: Its the implementation and what it does is returns the time point using<br />a lot of heuristics.<br /><br />JL: The point of the proposal is that the values that are returned are<br />inadequate, so there has to be a way to force a time point. <br /><br />KB: This has to do with VAMS and nothing to do with ASVA. <br /><br />JL: The FFT sampling that he got was very bad. <br /><br />KB: If you want to do FFT, you have to have very precise sampling. Its not<br />the language definition problem.<br /><br />JL: Those samples need to be under control for the checkers.<br /><br />KB: You want to dynamically control the accuracy of the cross statement.<br /><br />SL: The digital clock does not necessarily force the analog solver to solve<br />for that time. Its allowed by the LRM.<br /><br />KB: Is the $timer adequate to satisfy the requirement?<br /><br />JL: $timer is certainly a mechanism in the right direction. It could just be<br />a function call. It may be a function, not a VAMS language, but something<br />that allows to control the accuracy from within SV.<br /><br />KB: Probably then $timer needs to be put in SV first. So, sometimes you want<br />be exactly precise and at other times you do not want to that accurate.<br /><br />DN: Can you change the $timer dynamically just like @cross can be controlled<br />dynamically. <br /><br />HA: John, ED, do you have an opinion on this. This seems more of the larger<br />VAMS committee issue.<br /><br />ED: There will be no changes in SV for a year or two. There is a global<br />clocking is this in any way related to that.<br /><br />KB: $timer is a special function.<br /><br />SL: This has an effect on events and on solve points of analog solver, just<br />like @cross, @event.<br /><br />ED: If we connect a SV module to VAMS, then can you tie the SV event to an<br />analog event?<br /><br />KB: Their effect is the same. Used to execute processes.<br /><br />ED: Modules can receive events by reference and checkers can receive by<br />ports.<br /><br />SL: The definition of analog event and digital event is not the way the LRM<br />specifies. <br /><br />SC: Digital event is controlled by the digital part of the design.<br /><br />KB: The event does not occur in digital but is affected by digital event.<br /><br />SC: How can digital event affect the Mixed Signal simulation?<br /><br />KB: It does. <br /><br />PB: Does the @timer work for you. It could be something we could bring into<br />SV.<br /><br />JL: @timer would be great for simulator.<br /><br />JL: JL2, ability to access analog events within SV.<br /><br />KB: What does it meant to access an event?<br /><br />JL: This poses a lot of implementation problems. I was hoping to get a<br />function that will return an event. The basic idea is ideally SV specifies a<br />crossing and the function either return/does not return an event.<br /><br />SC: How will the function now wait for the event.<br /><br />KB: The function is an event. Fundamentally you want to be able to read the<br />value of access functions. <br /><br />JL: Just having a scalar port is not going to be sufficient. I want an access<br />function that allows me to have an accurate waveform. <br /><br />KB: Can you do the stuff you want in VAMS or not?<br /><br />JL: Yes, Then the trick is that you make them accessible from VAMS to SV.<br /><br />ED: Will do you most of the calculations on VAMS side and then receive the<br />final judgement on SV side. <br /><br />JL: That is possible, but would like all the checking functions in one<br />language. <br /><br />ED: If you get the timer functions and read them on real port. Is it not the<br /><br />same?<br /><br />JL: Yes, there are two sampling mechanisms that I want - timer functions<br />forcing time points and another is accepting analog time points.<br /><br />KB: If you want accurate point, you are going to pay the same amount no<br />matter how you do it. You want dynamic control over precision.<br /><br />JL: JL3. If there is some imprecision between analog and digital time<br />point, then I want better accuracy. As the analog clock has a different<br />value then the digital value. <br /><br />KB: In VHDL the analog time and the digital time has the same number of<br />bits.<br /><br />JL: I want to be able to get an accurate value with accurate time, which<br />does not have an artifical clock jitter.<br /><br />KB: I am afraid of getting these two ideas entangled together. First define<br />the language in the limit. <br /><br />JL: JL5, this is like corollary to JL1. This one talks about not forcing a<br />time point but just observing the values.<br /><br />KB: So, the proposal basically calls for two kinds of assignments, one is to<br />have a synchronized assignment and the other to not have synchronized<br />assignment. <br /><br />JL: That is not correct. The language is ambigious and the implementations<br />are probably not following the LRM.<br /> 

-- Main.AnandHimyanshu - 2009-11-03
Topic revision: r1 - 2009-11-03 - 21:57:58 - AnandHimyanshu
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