MeetingMinutes20091006 < VerilogAMS

VerilogAMS Web>AmsAssertions>RequirementsGatheringGroup>MeetingMinutes20091006 (2009-11-03, AnandHimyanshu) (raw view)EditAttach
Attendees:<br /><br />0000000000000001000010111100000000 Qamar Alam<br />1111111111111111111010111111101111 Himyanshu Anand<br />0111111110011111101110100011111111 Kenneth Bakalar<br />1111101010110110111011000011100011 Prabal Bhattacharya<br />0000000000000011000010100100001001 Sri Chandra<br />0111101111111111110110101111101111 Eduard Cerny<br />1110111000010110101110111110111111 Scott Cranston<br />0000000000000001000000000000000100 Dave Cronauer<br />0000000000001100000000011111100111 Dejan Nickovic<br />1101110111100100000000000000000000 Mike Demler<br />0000000000000000000000000000000000 Surrendra Dudani<br />1110000000111111111111001101111111 John Havlicek<br />1110001100100000000000000000000000 Kevin Jones (RGG Leader)<br />0000000111111111101110111111111111 Jim Lear<br />0000000000001110111000000000000000 Top Lertpanyavit<br />1111110110111111111111111011111111 Scott Little<br />0000000000000100000000000000000000 Erik Seligman<br />1010000000000000000000000000000000 David Sharrit<br />0000000100000000000000000000000000 Murtaza<br />0000000100000000000101100110000001 Martin O'Leary
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Decisions: 
   1 Voting on ASVA requirements complete.

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Action Items:<br />
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Details:

HA: Lets go through the various items voted upon and have a discussion on those.

KB: KB1 failed, minimize the changes. <br /><br />ED: We don't need this. We can always decide whether this is required.<br /><br />SC: KB3 assumes that SV will be a host language.<br /><br />KB: The point was just productions.<br /><br />SC: What is the definition of the host language.<br /><br />KB: Names, functions.<br /><br />SC: If KB3 does not restrict to SV then do not object to it.<br /><br />KB: KB4 is agreed upon.<br /><br />KB: KB5, All in agreement, ASVA as a superset of SVA and it should mean the same in both SV and ASVA. <br /><br />HA: Formula should not mean different things in ASVA (SV) and ASVA (VAMS). If they are different that's a recipe of disaster.<br /><br />KB: KB6,<br /><br />PB: Do we need a continous time, rather than a digital time?<br /><br />KB: The notation does not refer to simulator synchronization or interpolation.<br /><br />PB: The time refers to the time in analog solver?<br /><br />KB: No, it refers to the system being modeled.<br /><br />DN: I strongly agree with Ken. We will have assertions without explicit reference to time.<br /><br />PB: If it is meant that ASVA will be able to refer to time, but not impact the way the digital simulator works. We believe should be refered but that time should be extracted from the analog solver. It is possible from digital solver to force an exact point in analog solver.<br /><br />KB: In general there is no construct in VAMS that forces a time point.<br /><br />PB: Are you refering to be able to refer to that time in requirement KB6.<br /><br />DN: We need to specifically define what we mean by events in the language.<br /><br />KB: KB7, all agreed.<br /><br />KB: KB8, all agreed.<br /><br />KB: KB9, there was discussion about post-processing a wave form as opposed to online (on-the-fly). The expressions would be applicable to both forms of processing.<br /><br />DN: "As soon as the simulation...". I don't think that timing will be able to always meet this guarantee. The best you can say, is that you answer the question as close to the data point as possible.<br /><br />KB: You are making the same mistake about interpolation and synchronization.<br /><br />KB: We are not producing a "post-processing language"<br /><br />KB: KB10, I agree with SNPS and CDNS as well. Disagree in-principle with FSL. We need to be modest in our proposal and not expansive. <br /><br />JH: JH1, There has been some reflection on modules and checkers and whether we really need checkers. It may reduce checkers requirements. <br /><br />KB: Since all the ports the input ports, the expressions will be all in VAMS context. The elaborator will be in the SV.<br /><br />ED: The body of the checker is expanded in the context. They are not the same as module.<br /><br />JH: Checkers allow events to be hooked up. Modules do have event ports, they are hooked up by reference.<br /><br />ED: They cannot be expressions.<br /><br />JH: JH2, If the SV module/checker is instantiated in VAMS. The main intention was that if we are hooking up SV the port connection actual could be something be a part of SV in the mixed language model. We want to avoid the situation where disassembly/assembly is required.<br /><br />KB: My suggestion was to use a different model of connection.<br /><br />ED: Does it not depend on how you deal with two heirarchies. If its unified, then why can you not solve it.<br /><br />KB: The VAMS parser needs to understand that.<br /><br />ED: What if the two parsers are closely integrated?<br /><br />KB: Yes, it could be done. But that's a large job to do that.<br /><br />JH: It will be more productive to craft some details and re-evaluate it. <br /><br />KB: If its not a legal VAMS connect expression. You have to tell me how to read it. <br /><br />ML: There is some disagreement on this. It sounds like we need to get some more technical details and discuss this later.<br /><br />JH: JH3, no disagreement. This was the motivating capability to bring the checkers.<br /><br />JH: JH4, Suppose the actual is an integral in SV and that is legal in VAMS. But the formal is not a VAMS type but is legal in SV but they are assignment compatible. <br /><br />KB: It may be an in-port or out-port. If its an in-port the assignment belongs to SV if its out-port then it belongs to VAMS.<br /><br />ED: Are we not restricting everything to input only?<br /><br />KB: I don't think so. But we could. That yes, most of us are thinking about inputs.<br /><br />JH: Even if there is an ouput, SV will do the assignment compatible. And the values that come out will be interpreted by VAMS.<br /><br />KB: Is everything packed? Arrays?<br /><br />JH: The syntax matches for packed arrays with unpacked arrays?<br /><br />KB: VAMS has no notion of packed/unpacked.<br /><br />JH: If they are packed they are compatible. <br /><br />JH: JH6, Vector of wreal will be interesting.<br /><br />SC: Does this mean we have to add wreal to SV? Is that a bad thing?<br /><br />JL: Yes, that's a bad thing.<br /><br />JL: JL1, Wanted an ability to force a time point in VAMS from SV.<br /><br />ML: Why is it required?<br /><br />KB: The analog simulator gives the value at the time, how it goes about getting the point is upto the simulator.<br /><br />JL: The level of accuracy based on the heuristics is never satisfactory. You<br />always have to force a time point, particularly for a FFT.

-- Main.AnandHimyanshu - 2009-11-03
Topic revision: r1 - 2009-11-03 - 21:53:31 - AnandHimyanshu
VerilogAMS