MeetingMinutes20090923 < VerilogAMS

VerilogAMS Web>AmsAssertions>RequirementsGatheringGroup>MeetingMinutes20090923 (2009-11-03, AnandHimyanshu) (raw view)EditAttach
Attendees:<br /><br />00000000000000010000101111000000 Qamar Alam<br />11111111111111111110101111111011 Himyanshu Anand<br />01111111100111111011101000111111 Kenneth Bakalar<br />11111010101101101110110000111000 Prabal Bhattacharya<br />00000000000000110000101001000010 Sri Chandra<br />01111011111111111101101011111011 Eduard Cerny<br />11101110000101101011101111101111 Scott Cranston<br />00000000000000010000000000000001 Dave Cronauer<br />00000000000011000000000111111001 Dejan Nickovic<br />11011101111001000000000000000000 Mike Demler<br />00000000000000000000000000000000 Surrendra Dudani<br />11100000001111111111110011011111 John Havlicek<br />11100011001000000000000000000000 Kevin Jones (RGG Leader)<br />00000001111111111011101111111111 Jim Lear<br />00000000000011101110000000000000 Top Lertpanyavit<br />11111101101111111111111110111111 Scott Little<br />00000000000001000000000000000000 Erik Seligman<br />10100000000000000000000000000000 David Sharrit<br />00000001000000000000000000000000 Murtaza<br />00000001000000000001011001100000 Martin O'Leary<br /><br />Decisions:<br /><br />Action Items:<br /><br />Details:<br /><br />DN: Do not want to vote, uncomfortable.<br /><br />JH: Accellera members are allowed to vote.<br /><br />KB: Yes, that is correct.<br /><br />JH: Is anyone contemplating changing the requirement.<br /><br />HA: Four companies.<br /><br />KB: What if inconsistent or redundant?<br /><br />ED: Can it be sorted out after the vote?<br /><br />JH: If there are redundancies and overlaps, they are fine. If they are inconsistenties then we can sort it out later. But, waiting for the vote will delay the vote.<br /><br />KB: What happens if the requirements are voted upon. <br /><br />HA: Yes, they will be reference points.<br /><br />KB: Do we have to justify the negative votes?<br /><br />JH: Yes, some explanation with a down vote. That is also what Sri suggested.<br /><br />DN: Are, we allowed to see the votes.<br /><br />JH: They can see and should be allowed to provide their feedback.<br /><br />JL: Some of them may not be accepted. What are the proposals that will not be accepted.<br /><br />HA: Can we wait for the vote for the feedback?<br /><br />KB: Things I am going to object are specific language features. Doesn't make sense to have a language feature as requirement.<br /><br />JL: What is your bottom line here?<br /><br />KB: Some of them are requirements and some are language features.<br /><br />KB: Discussion on Scott's Cranston email.<br /><br />JH: Collisions during elaboration need to be resolved and is easier.<br /><br />KB: Not enough to say, in some universe it can be done.<br /><br />SC: What's wrong with saying it is being done in SV?<br /><br />JL: Shouldn't each actual have designated scope to only VAMS operations and reference and other actual has only SV references.<br /><br />ED: If you have unified hierarchy.<br /><br />JH: We need to follow the definition of bind that those port expressions be interpreted from the point of target. Are there packages in the model. How do you reference a package. ED has a point there.<br /><br />KB: The elaboration can happen repeatedly and during runtime.<br /><br />ED: What you are saying is an implementation issue. Because you are assuming two different parsers.<br /><br />SC: What is evaluate you are talking about?<br /><br />KB: Evaluate is assigning values.<br /><br />JH: That definition does not apply to checkers. The mentor model of evaluating is awkward for evaluating the port expressions.<br /><br />SC: Yes.<br /><br />ED: Also, checker ports are by substitution by expression, not by name.<br /><br />JH: My point was not suggest limit the checkers.<br /><br />KB: You can require something to be untyped. <br /><br />JH: All the sequences and properties are untyped arguments. And there is flexibility to have those. <br /><br />KB: How much apparatus are we going to put in VAMS for properties?<br /><br />JH: My idea was to write those in SV containers.<br /><br />KB: Then one of my requirements does not make sense. Evaluation of an assertion in the context.<br /><br />JL: If we have checkers, then they could be reused in other places. Checkers should be agnostic and should be legal SV port and should not know anything beyond <br /><br />-- Main.AnandHimyanshu - 2009-11-03
Topic revision: r1 - 2009-11-03 - 21:38:45 - AnandHimyanshu
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