MeetingMinutes20090203 < VerilogAMS

VerilogAMS Web>AmsAssertions>RequirementsGatheringGroup>MeetingMinutes20090203 (2009-02-04, AnandHimyanshu) (raw view)EditAttach
Attendees:
Scott Cranston, Mike Demler, Scott Little, John Havlicek, Himyanshu Anand, Prabal Bhattacharya, Kevin Jones, Ken Bakalar, Ed Cerny

Decisions:
--------------
   * Section owners assigned for requirements gathering group.

Action Items:
------------------
   * Background information template on Twiki [Himyanshu]
   * Requirements document template on Twiki [Himyanshu]
   * Background information to be filled by members [All]
   * Sections to be filled by members [All]

Details:
----------

KJ: Draft was put together. Capture all of the ideas people have brought up so far. Open for discussion. Some adjustments and people taking ownership.

KB: What level of expertise do we have here.

KJ: Some of the initial 

KB: Product manager at Mentor Graphics. Training is in CS (back in 1968). Degree in applied mathematics, and bio-medical engineering. Mechanical design. VHDL design and subsequently in the design with VHDL language. Language lawyer.

Ed: Come from a simulation/formal verification of digital systems. Testing and timing analysis. 8 years in Synopsys, 8 years professor in Montreal. System Verilog assertions.

KJ: Template for Twiki and places where people can fill in.

SC: Can everyone can edit this?

HA: Yes, you just sign up.

MD: Interaction between digital/analog engine. (Section 10)

KJ: Existing digital tools, what is the interaction with the analog simulation engine. The initial sections articulate our view of the problems and the later sections relate to the language and the final section details with 

SC: Take 2.

KJ: However much you think is required to make the work.

SC: Start on the intial ones and the later ones would change on what we get from initial ones.

Ken: Take 8, come up with the choices/requirements.

MD: Product architect and pretty good knowledge of analog simulators. Section 4 and 3.

PB: Analog part of the AMS simulator (10) and will talk both about digital/analog engine.

KJ: Section 1. Section 6 all. High speed and power guys.

PB: Some sections logically precedes others. 

KJ: Put in first section, so that we have something.

SL: Take 5. What are you looking for there.

KJ: All we really need to do is dense time and we are done, is what we have heard till now. But, who is the person who really does that verification.

KJ: Take 11

PB: 8 is the heavier

KB: Need to have decision quickly.

MD: A week, but next week is busy. Late next week looks realistic.

HA: Will put the Twiki Template. Need to send a request to support at eda org.

KJ: Let people work independently. 

JH: Will be a lurker on 8.

KJ: Good that everyone has signed up something. Then pick a section.


-- Main.AnandHimyanshu - 04 Feb 2009
Topic revision: r1 - 2009-02-04 - 17:49:27 - AnandHimyanshu
VerilogAMS