MeetingMinutes20090120 < VerilogAMS

VerilogAMS Web>AmsAssertions>RequirementsGatheringGroup>MeetingMinutes20090120 (2009-01-26, AnandHimyanshu) (raw view)EditAttach
Attendees:
Scott Cranston, Mike Demler, Scott Little, John Havlicek, Himyanshu Anand, David Sharrit, Prabal Bhattacharya, Kevin Jones.

Decisions:
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   * Kevin Jones to lead the requirements group.
   * Time Change: 7 am Pacific Time, weekly frequency (Starting from Feb 3rd, 2009)

Action Items:
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   * Kevin will send an initial draft of requirements document by end of the week.
   * Others will go through that document and add to the relevant sections which can be discussed in the next meeting.

Details:
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MD: I can contribute to the classes of assertions, similar to Taxonomy on my blog.

KJ: What is the relationship between current digital and proposed language? What type of problems are we going to solve?

PB: Good initial document. Use case from FSL.

KJ: We have also provided use cases. What each of us brings to the table? So that we do not have wasted talent.

HA: Equivalence checking, symbolic simulation based formal methods.

SL: Semi-formal methods, product team, analog and mixed signal analog blocks. Largely formal methods, not a strong deep knowledge analog methods.

JH: Mathematics (PhD), Alan Emerson research model checking, formal verification with applications to semi-conductors. Worked with Carl Pixley and worked with PSL committee. System Verilog Assertion development in Accellera and IEEE. Formal property language unlocks a lot of value. This has been beneficial in digital and would like to see the same happen in analog world.

KJ: Oxford, semantic models, specification languages in software domain, appropriate semantic models and specification (Z language). Research labs, algebraic semantics and getting formal methods to user community. 10 years at Rambus, to verify high speed analog designs. This was an IP company, worked with many flows. Worked on formal approaches for analog verification. Trying to find the right balance of digital and analog tools. Users mindset should be considered. Green Plug, digital controlled power supply company. Designers here have strong notions of what systems properties are. Less of everything but maybe that's good.

MD: 18 years, analog circuit designers. Then into sales and marketing. Startup in 1997, Verilog-A was just coming along the scene. Then into Synopsys. The verification groups at Synopsys are separate into digital and analog groups. About two years ago they were combined. The idea emerged to build an equivalent to VMM in analog. Exploring ideas. I can bring an analog designers state of mind, as well as good insight into how these things will work in EDA and practical world.

PB: With Cadence for last 13 years. Software with electrical background. Started working on AMS Designer for about last 9 years. Over the last year or so, interested by development of digital and analog coming together. Simulator development. Understand user requirements and how they fit into the languages and the simulators.

DS: With Tiburon. Was with HP, Agilient for the last 30 years or so. Took early retirement and joined Tiburon Design. Currently in the process to educate myself with System Verilog. Still in a learning mode as well.

SC: Almost 20 years with Cadence now. Worked on Verilog-XL, and NC-Verilog. Also, working on AMS simulations. Interested in new approaches to solving mixed signal.

KJ: Provide some structure is a good worthwhile first goal.

JH: Someone should volunteer to lead and then delegate the tasks.

SL: Would you be willing to volunteer?

KJ: I would be willing to do whatever it takes to get this working.

JH: Lets choose KJ as the lead.

KJ: What is the level of participation and commitment from others. This will allow us to define the timeline. I can do 0.5 day@week.

HA: I can do a day@week.

SL: 1-2 days@week. Most of the work that can come out of FSL was done by me and then reviewed by Himyanshu and John.

JH: 0.5 day@week. Reviewing the documents/emails.

PB: Couple of hours@week.

DS: Reading minutes and attending meetings. 4-5 hrs@week.

MD: Probably about 0.5-1 day@week.

SC: 0.5 day@week.

KJ: About 3 hours a week. Do we have any external time constraints?

SL: Unless we go very slow or VAMS go very fast, this may not be an issue.

PB: How do we interface with the larger community and make sure we are in sync. We can invite someone like Sri once in a while to the meeting.

KJ: Very good idea.

PB: Can we change the time.

Time Change: 7 am Pacific Time, weekly frequency.

HA: What do we want to do in the next meeting.

KJ: Extend the outline, build a draft and share it with others for feedback.

KJ: What about minutes, email aliasing, etc.

HA: We will continue doing the minutes.

JH: In the past, we have not made public the minutes, unless really needed.

HA: Put the minutes on the Twiki with action items.

KJ: Will send the initial documents by the end of week. 

-- Main.AnandHimyanshu - 26 Jan 2009
Topic revision: r1 - 2009-01-26 - 18:18:24 - AnandHimyanshu
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