(r4) AmsExamplesBEDM < VerilogAMS

VerilogAMS Web>AmsExamples>AmsExamplesBEDM (revision 4) (raw view)~~EditAttach~~

---+ Basic Electrical Device Models (BEDM)
| *Type* | *Description* | *Source* |
| [[#Resistor][Resistor]] | Single branch resistor model with bi-directional termainals | [[%ATTACHURL%/resistor.va][resistor.va]] |
| [[#Capacitor][Capacitor]] | Single branch capacitor model with bi-directional terminals | [[%ATTACHURL%/capacitor.va][capacitor.va]] |
| [[#Inductor][Inductor]] | Single branch inductor model with bi-directional terminals | [[%ATTACHURL%/inductor.va][inductor.va]] |
| [[#VCVS][VCVS]] | Ideal voltage-controlled voltage source | [[%ATTACHURL%/vcvs.va][vcvs.va]] |
| [[#CCCS][CCCS]] | Ideal current-controlled current source | [[%ATTACHURL%/cccs.va][cccs.va]] |
| [[#IdealSwitch][Ideal Switch]] | Ideal switch with control terminal | [[%ATTACHURL%/ideal_switch.va][ideal_switch.va]] |
| [[#3PVS][3-Phase Voltage Source]] | 3 phase voltage source with amplitude and frequency control | [[%ATTACHURL%/3ph_vs.va][3ph_vs.va]] |
| [[#VTWG][Voltage Triangle Wave Generator]] | Voltage triangle waveform generator | [[%ATTACHURL%/V_triangle_generator.va][V_triangle_generator.va]] |
| [[#VSWG][Voltage Sine Wave Generator]] | Voltage sine waveform generator | [[%ATTACHURL%/V_sine_generator.va][V_sine_generator.va]] |
---++ <a name="Resistor">Resistor</a>
| *Module Name* | res |
| *Terminals* | p: positive terminal : inout electrical<br />n: negative terminal : inout electrical |
| *Parameter* | r: resistance = 0 |
| *Spectre Testbench* | [[%ATTACHURL%/rc.scs][rc.scs]] |
| *HSPICE Testbench* | |
---++ <a name="Capacitor">Capacitor</a>
| *Module Name* | cap |
| *Terminals* | p: positive terminal : inout electrical<br />n: negative terminal : inout electrical |
| *Parameter* | c: capacitance = 0 |
| *Spectre Testbench* | [[%ATTACHURL%/rc.scs][rc.scs]] |
| *HSPICE Testbench* | |
---++ <a name="Inductor">Inductor</a>
| *Module Name* | ind |
| *Terminals* | p: positive terminal : inout electrical<br />n: negative terminal : inout electrical |
| *Parameter* | l: inductance = 0 |
| *Spectre Testbench* | [[%ATTACHURL%/inductor.scs][inductor.scs]] |
| *HSPICE Testbench* | |
---++ <a name="VCVS">Voltage-Controlled Voltage Source</a>
| *Module Name* | vcvs |
| *Terminals* | p: positive output terminal : inout electrical<br />n: negative output terminal : inout electrical<br />pc: positive control terminal : inout electrical<br />n: negative control terminal : inout electrical |
| *Parameter* | gain: gain = 0 |
| *Spectre Testbench* | [[%ATTACHURL%/vcvs.scs][vcvs.scs]] |
| *HSPICE Testbench* | |
---++ <a name="CCCS">Current-Controlled Current Source</a>
| *Module Name* | cccs |
| *Terminals* | p: positive output terminal : inout electrical<br />n: negative output terminal : inout electrical<br />pc: positive control terminal : inout electrical<br />n: negative control terminal : inout electrical |
| *Parameter* | gain: gain = 0 |
| *Spectre Testbench* | |
| *HSPICE Testbench* | |
---++ <a name="IdealSwitch">Ideal Switch</a>
| *Module Name* | ideal_switch |
| *Terminals* | p: positive output terminal : inout electrical<br />n: negative output terminal : inout electrical<br />pc: positive switch control terminal : input voltage<br />n: negative switch control terminal : input voltage |
| *Parameter* | ctr_vth: switch state control threshold voltage = 1<br />switch_type: switch type selector = 0<br /> <table cellspacing="1" cellpadding="0" border="1"> <tbody> <tr> <td></td> <td>switch_type = 0</td> <td>switch_type = 1</td> </tr> <tr> <td>V(control) &gt;= ctr_vth</td> <td>closed</td> <td>open</td> </tr> <tr> <td>V(control) &lt; ctr_vth</td> <td>open</td> <td>closed</td> </tr> </tbody> </table> |
| *Spectre Testbench* | |
| *HSPICE Testbench* | |
---++ <a name="3PVS">3-Phase Voltage Source</a>
| *Module Name* | vsrc_3ph |
| *Terminals* | amp: amplitude control terminal : input voltage<br />fre: frequency control terminal : input voltage<br />gnd: reference terminal for amp and fre terminal : input voltage<br />pha: terminal for phase a : output voltage<br />phb: terminal for phase b : output voltage<br />phc: terminal for phase c : output voltage<br />phn: terminal for center of all phases : output voltage |
| *Parameter* | ka: coefficient on magnitude = 1<br />kf: coefficient on frequency = 1<br />phi: phase difference = 0 |
| *Spectre Testbench* | |
| *HSPICE Testbench* | |
---++ <a name="VTWG">Voltage Triangle Waveform Generator</a>
| *Module Name* | V_triangle_generator |
| *Terminals* | out: output terminal : output voltage |
| *Parameter* | period: period of triangle = 10ns<br />ampl: amplitude of triangle = 1 |
| *Spectre Testbench* | |
| *HSPICE Testbench* | |
---++ <a name="VSWG">Voltage Sine Waveform Generator</a>
| *Module Name* | V_sine_generator |
| *Terminals* | out: output terminal : output voltage |
| *Parameter* | freq: frequency of sine signal<br />ampl: amplitude of sine = 1<br />offset: dc offset = 0 |
| *Spectre Testbench* | |
| *HSPICE Testbench* | |

-- Main.DavidMiller - 2011-02-24

Attachments

I	Attachment	Action	Size	Date	Who	Comment
va	3ph_vs.va	manage	1.7 K	2012-09-14 - 15:36	DavidMiller	3 phase voltage source with amplitude and frequency control
va	V_sine_generator.va	manage	0.7 K	2012-09-14 - 15:36	DavidMiller	Voltage sine waveform generator
va	V_triangle_generator.va	manage	0.9 K	2012-09-14 - 15:37	DavidMiller	Voltage triangle waveform generator
va	capacitor.va	manage	0.5 K	2012-09-14 - 15:37	DavidMiller	Single branch capacitor model with bi-directional terminals
va	cccs.va	manage	0.5 K	2012-09-14 - 15:37	DavidMiller	Ideal current-controlled current source
va	ideal_switch.va	manage	0.9 K	2012-09-14 - 15:37	DavidMiller	Ideal switch with control terminal
scs	inductor.scs	manage	0.8 K	2012-09-19 - 14:36	DavidMiller	Inductor testbench - Spectre style
va	inductor.va	manage	0.5 K	2012-09-14 - 15:38	DavidMiller	Single branch inductor model with bi-directional terminals
scs	rc.scs	manage	0.8 K	2012-09-19 - 14:37	DavidMiller	Simple RC testbench - Spectre style
va	resistor.va	manage	0.5 K	2012-09-14 - 15:38	DavidMiller	Single branch resistor model with bi-directional termainals
scs	vcvs.scs	manage	0.7 K	2012-09-19 - 15:41	DavidMiller	VCVS Testbench - Spectre style
va	vcvs.va	manage	0.5 K	2012-09-14 - 15:38	DavidMiller	Ideal voltage-controlled voltage source

Topic revision: r1 - 2012-09-19 - 15:43:49 - TWikiGuest

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