VerilogAMS Web>AmsExamples>AmsExamplesBEDM (revision 2)~~EditAttach~~

Basic Electrical Device Models (BEDM)

Type	Description	Source
Resistor	Single branch resistor model with bi-directional termainals	resistor.va
Capacitor	Single branch capacitor model with bi-directional terminals	capacitor.va
Inductor	Single branch inductor model with bi-directional terminals	inductor.va
VCVS	Ideal voltage-controlled voltage source	vcvs.va
CCCS	Ideal current-controlled current source	cccs.va
Ideal Switch	Ideal switch with control terminal	ideal_switch.va
3-Phase Voltage Source	3 phase voltage source with amplitude and frequency control	3ph_vs.va
Voltage Triangle Wave Generator	Voltage triangle waveform generator	V_triangle_generator.va
Voltage Sine Wave Generator	Voltage sine waveform generator	V_sine_generator.va

Resistor

Module Name	res
Terminals	p: positive terminal : inout electrical n: negative terminal : inout electrical
Parameter	r: resistance = 0
Spectre Testbench	rc.scs
HSPICE Testbench

Capacitor

Module Name	cap
Terminals	p: positive terminal : inout electrical n: negative terminal : inout electrical
Parameter	c: capacitance = 0
Spectre Testbench	rc.scs
HSPICE Testbench

Inductor

Module Name	ind
Terminals	p: positive terminal : inout electrical n: negative terminal : inout electrical
Parameter	l: inductance = 0
Spectre Testbench	inductor.scs
HSPICE Testbench

Voltage-Controlled Voltage Source

Module Name	vcvs
Terminals	p: positive output terminal : inout electrical n: negative output terminal : inout electrical pc: positive control terminal : inout electrical n: negative control terminal : inout electrical
Parameter	gain: gain = 0
Spectre Testbench	vcvs.scs
HSPICE Testbench

Current-Controlled Current Source

Module Name	cccs
Terminals	p: positive output terminal : inout electrical n: negative output terminal : inout electrical pc: positive control terminal : inout electrical n: negative control terminal : inout electrical
Parameter	gain: gain = 0
Spectre Testbench
HSPICE Testbench

Ideal Switch

Module Name

ideal_switch

Terminals

p: positive output terminal : inout electrical
n: negative output terminal : inout electrical
pc: positive switch control terminal : input voltage
n: negative switch control terminal : input voltage

Parameter

ctr_vth: switch state control threshold voltage = 1
switch_type: switch type selector = 0

	switch_type = 0	switch_type = 1
V(control) >= ctr_vth	closed	open
V(control) < ctr_vth	open	closed

Spectre Testbench

HSPICE Testbench

3-Phase Voltage Source

Module Name	vsrc_3ph
Terminals	amp: amplitude control terminal : input voltage fre: frequency control terminal : input voltage gnd: reference terminal for amp and fre terminal : input voltage pha: terminal for phase a : output voltage phb: terminal for phase b : output voltage phc: terminal for phase c : output voltage phn: terminal for center of all phases : output voltage
Parameter	ka: coefficient on magnitude = 1 kf: coefficient on frequency = 1 phi: phase difference = 0
Spectre Testbench
HSPICE Testbench

Voltage Triangle Waveform Generator

Module Name	V_triangle_generator
Terminals	out: output terminal : output voltage
Parameter	period: period of triangle = 10ns ampl: amplitude of triangle = 1
Spectre Testbench
HSPICE Testbench

Voltage Sine Waveform Generator

Module Name	V_sine_generator
Terminals	out: output terminal : output voltage
Parameter	freq: frequency of sine signal ampl: amplitude of sine = 1 offset: dc offset = 0
Spectre Testbench
HSPICE Testbench

-- DavidMiller - 2011-02-24

Attachments

I	Attachment	Action	Size	Date	Who	Comment
va	3ph_vs.va	manage	1.7 K	2012-09-14 - 15:36	DavidMiller	3 phase voltage source with amplitude and frequency control
va	V_sine_generator.va	manage	0.7 K	2012-09-14 - 15:36	DavidMiller	Voltage sine waveform generator
va	V_triangle_generator.va	manage	0.9 K	2012-09-14 - 15:37	DavidMiller	Voltage triangle waveform generator
va	capacitor.va	manage	0.5 K	2012-09-14 - 15:37	DavidMiller	Single branch capacitor model with bi-directional terminals
va	cccs.va	manage	0.5 K	2012-09-14 - 15:37	DavidMiller	Ideal current-controlled current source
va	ideal_switch.va	manage	0.9 K	2012-09-14 - 15:37	DavidMiller	Ideal switch with control terminal
scs	inductor.scs	manage	0.8 K	2012-09-19 - 14:36	DavidMiller	Inductor testbench - Spectre style
va	inductor.va	manage	0.5 K	2012-09-14 - 15:38	DavidMiller	Single branch inductor model with bi-directional terminals
scs	rc.scs	manage	0.8 K	2012-09-19 - 14:37	DavidMiller	Simple RC testbench - Spectre style
va	resistor.va	manage	0.5 K	2012-09-14 - 15:38	DavidMiller	Single branch resistor model with bi-directional termainals
scs	vcvs.scs	manage	0.7 K	2012-09-19 - 15:41	DavidMiller	VCVS Testbench - Spectre style
va	vcvs.va	manage	0.5 K	2012-09-14 - 15:38	DavidMiller	Ideal voltage-controlled voltage source

Topic revision: r1 - 2012-09-19 - 15:43:49 - TWikiGuest

VerilogAMS