FSMLanguage < P1076

P1076 Web>VHDLProposals>FSMLanguage (2017-04-02, PatrickLehmann) (raw view)EditAttach
---+!! Embedded FSM Language
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---++!! Proposal Details

| *Authors*        | [[Main.PatrickLehmann][Patrick Lehmann]] |
| *Date Proposed*  | 2017-04-02                               |
| *Last Updated*   | 2017-04-02                               |
| *Focus*          | simulation and synthesis                |
| *LCS*            | TBD                                      |

---++
%TOC%
---++

---++ Summary
State machine are currently written in a 1-, 2- or 3 process pattern using regular VHDL process statements. It proposal presents
a concurrent statement that describes a state machine with various extra features which are hard to implement in normal process
based FSMs.


---++ Current Situation
There are three accepted VHDL coding pattern to describe a state machine in VHDL:
   1 *1 process pattern* %BR%
   1 *2 process pattern* %BR%
   1 *3 process pattern* %BR%


---++ Requirement
The new =statemachine= statement shall support the following features:
   * Single clocked
   * Synchronous and asynchronous reset
   * Required default assignments (no latches)
   * Clear transitions on goto
   * Entry and exit handlers
   * Selectable encoding via attribute
   * Supports Mealy and Moore type
   * Supports init (FPGA) and reset state (both)

---+++ Planned features

   * Sub state machines
   * Virtual states
   * State machine to state machine communication


---++ Use Cases
%GREEN%Add some use cases.%ENDCOLOR%

---++ Implementation details

*New reserved words:*
   * statemachine
   * state
   * entry
   * goto


---++ Code Examples

<pre>
statemachine myFSM is
  configuration (
    Clock =>     clk,
    SyncReset => rst,
    -- ASyncReset => rst_a
    InitialState => IDLE,
    Reset state => IDLE
  );
  default (
    LeaveIdle => ‘0’,
    Working => ‘0’,
    ErrorRaised => ‘0’
  );
  state IDLE is
    goto WORKING;
    on exit to (all)
      LeaveIdle <= ‘1’;
    end on exit;
  end state;

  state WORKINK is
    Working <= ‘1’;
    goto ERROR when (err = ‘1’);
  end state;

  state ERROR is
    on entry from (WORKING)
      ErrorRaised <= ‘1’;
    end on entry;
  end state;
end statemachine;
</pre>


---++ Arguments FOR

   * Clean syntax
   * Lower complexity for big FSMs compared to process pattern
   * No pattern matching in VHDL tools to find FSMs


---++ Arguments AGAINST

   * 4 new reserved words


---++ General Comments


%COMMENT%
---++ Supporters

   * [[Main.PatrickLehmann][Patrick Lehmann]] - 2017-04-02
   * _Add your signature here to indicate your support for the proposal_

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Topic revision: r2 - 2017-04-02 - 22:11:18 - PatrickLehmann
P1076